f3d9cb43a596f8fd90263d0cfaebff33da5c2903
[riscv-tests.git] / debug / targets / freedom-e300-sim / openocd.cfg
1 adapter_khz 10000
2
3 source [find interface/jtag_vpi.cfg]
4 jtag_vpi_set_port $::env(JTAG_VPI_PORT)
5
6 set _CHIPNAME riscv
7 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
8
9 set _TARGETNAME $_CHIPNAME.cpu
10 target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
11
12 init
13 halt