isa/macros/simplev/sv_test_macros.h

   1 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
   2   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
   3 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
   4   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
   5
   6 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
   7         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
   8         csrrw  x0, 0x4c0, x1
   9
  10 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
  11         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
  12         csrrw  x0, 0x4c8, x1
  13
  14 #define SET_SV_2CSRS( c1, c2 ) \
  15         li     x1, c1 | ((c2)<<16U); \
  16         csrrw  x0, 0x4c0, x1
  17
  18 #define SET_SV_3CSRS( c1, c2 , c3 ) \
  19         li     x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
  20         csrrw  x0, 0x4c0, x1
  21
  22 #define SET_SV_2PREDCSRS( c1, c2 ) \
  23         li     x1, c1 | ((c2)<<16U); \
  24         csrrw  x0, 0x4c8, x1
  25
  26 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
  27 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
  28
  29 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
  30 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
  31
  32 #define SV_LD_DATA( reg, from, offs ) \
  33         la      x1, from; \
  34         lw      reg, offs(x1)
  35
  36 #define SV_LDD_DATA( reg, from, offs ) \
  37         la      x1, from; \
  38         ld      reg, offs(x1)
  39
  40 #define SV_FLD_DATA( reg, from, offs ) \
  41         la      x1, from; \
  42         fld     reg, offs(x1)
  43
  44 #define TEST_SV_IMM( reg, imm ) \
  45         li      t6, ((imm) & 0xffffffffffffffff); \
  46         bne     reg, t6, fail
  47
  48 #define TEST_SV_FD( flags, freg, from, offs ) \
  49         fsflags x2, x0; \
  50         li      x1, flags; \
  51         bne     x2, x1, fail; \
  52         la      x1, from; \
  53         ld      x1, offs(x1); \
  54         fmv.x.d x2, freg; \
  55         bne     x2, x1, fail
  56
  57 #define SV_W_DFLT 0
  58 #define SV_W_8BIT 1
  59 #define SV_W_16BIT 2
  60 #define SV_W_32BIT 3