isa/macros/simplev/sv_test_macros.h

   1 #define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
   2   (reg0 | (reg1<<8) | (reg2<<8) | \
   3    (shape0<<24) | (shape0<<26) | (shape0<<28))
   4
   5 #define SV_SHAPE_PERM_XYZ 0
   6 #define SV_SHAPE_PERM_XZY 1
   7 #define SV_SHAPE_PERM_YXZ 2
   8 #define SV_SHAPE_PERM_YZX 3
   9 #define SV_SHAPE_PERM_ZXY 4
  10 #define SV_SHAPE_PERM_ZYX 5
  11
  12 #define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \
  13   ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \
  14    ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) )
  15
  16
  17 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
  18   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
  19 #define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
  20   (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
  21
  22 #define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
  23         li     x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \
  24         csrrw  x0, 0x4f7, x1
  25
  26 #define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \
  27         li     x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
  28         csrrw  x0, 0x4f8, x1
  29
  30 #define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
  31         li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
  32         csrrw  x0, 0x4c0, x1
  33
  34 #define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
  35         li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
  36         csrrw  x0, 0x4c8, x1
  37
  38 #define SET_SV_2CSRS( c1, c2 ) \
  39         li     x1, c1 | ((c2)<<16U); \
  40         csrrw  x0, 0x4c0, x1
  41
  42 #define SET_SV_3CSRS( c1, c2 , c3 ) \
  43         li     x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
  44         csrrw  x0, 0x4c0, x1
  45
  46 #define SET_SV_2PREDCSRS( c1, c2 ) \
  47         li     x1, c1 | ((c2)<<16U); \
  48         csrrw  x0, 0x4c8, x1
  49
  50 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
  51 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0
  52
  53 #define SET_SV_MVL( val ) csrrwi   x0, 0x4f1, (val-1)
  54 #define SET_SV_VL( val )  csrrwi   x0, 0x4f0, (val-1)
  55
  56 #define SV_LD_DATA( reg, from, offs ) \
  57         la      x1, from; \
  58         lw      reg, offs(x1)
  59
  60 #define SV_LDD_DATA( reg, from, offs ) \
  61         la      x1, from; \
  62         ld      reg, offs(x1)
  63
  64 #define SV_FLD_DATA( reg, from, offs ) \
  65         la      x1, from; \
  66         fld     reg, offs(x1)
  67
  68 #define SV_FLW_DATA( reg, from, offs ) \
  69         la      x1, from; \
  70         flw     reg, offs(x1)
  71
  72 #define TEST_SV_IMM( reg, imm ) \
  73         li      t6, ((imm) & 0xffffffffffffffff); \
  74         bne     reg, t6, fail
  75
  76 #define TEST_SV_FD( flags, freg, from, offs ) \
  77         fsflags x2, x0; \
  78         li      x1, flags; \
  79         bne     x2, x1, fail; \
  80         la      x1, from; \
  81         ld      x1, offs(x1); \
  82         fmv.x.d x2, freg; \
  83         bne     x2, x1, fail
  84
  85 #define TEST_SV_FW( flags, freg, from, offs ) \
  86         fsflags x2, x0; \
  87         li      x1, flags; \
  88         bne     x2, x1, fail; \
  89         la      x1, from; \
  90         lw      x1, offs(x1); \
  91         fmv.x.s x2, freg; \
  92         bne     x2, x1, fail
  93
  94 #define SV_W_DFLT 0
  95 #define SV_W_8BIT 1
  96 #define SV_W_16BIT 2
  97 #define SV_W_32BIT 3