isa/rv64mi/ma_addr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_addr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned ld/st trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64M
  14 RVTEST_CODE_BEGIN
  15
  16   .option norvc
  17
  18   la s0, data
  19
  20   # indicate it's a load test
  21   li s1, CAUSE_MISALIGNED_LOAD
  22
  23 #define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1)))
  24
  25 /* Check that a misaligned load either writes the correct value, or
  26    takes an exception and performs no writeback.  */
  27 #define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \
  28   li TESTNUM, testnum; \
  29   la t2, 1f; \
  30   addi t1, base, offset; \
  31   insn t1, offset(base); \
  32   li t2, res; \
  33   bne t1, t2, fail; \
  34 1:
  35
  36   MISALIGNED_LOAD_TEST(2,  lh,  s0, 1, SEXT(0xbbcc, 16))
  37   MISALIGNED_LOAD_TEST(3,  lhu, s0, 1, 0xbbcc)
  38   MISALIGNED_LOAD_TEST(4,  lw,  s0, 1, SEXT(0x99aabbcc, 32))
  39   MISALIGNED_LOAD_TEST(5,  lw,  s0, 2, SEXT(0x8899aabb, 32))
  40   MISALIGNED_LOAD_TEST(6,  lw,  s0, 3, SEXT(0x778899aa, 32))
  41
  42 #if __riscv_xlen == 64
  43   MISALIGNED_LOAD_TEST(7,  lwu, s0, 1, 0x99aabbcc)
  44   MISALIGNED_LOAD_TEST(8,  lwu, s0, 2, 0x8899aabb)
  45   MISALIGNED_LOAD_TEST(9,  lwu, s0, 3, 0x778899aa)
  46
  47   MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc)
  48   MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb)
  49   MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa)
  50   MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899)
  51   MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788)
  52   MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677)
  53   MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566)
  54 #endif
  55
  56   # indicate it's a store test
  57   li s1, CAUSE_MISALIGNED_STORE
  58
  59 /* Check that a misaligned store has some effect and takes no exception,
  60    or takes no effect and generates an exception.  This is not very
  61    thorough.  */
  62 #define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \
  63   li TESTNUM, testnum; \
  64   la t2, 1f; \
  65   addi t1, base, offset; \
  66   insn x0, offset(base); \
  67   lb t1, (offset - 1)(base); \
  68   beqz t1, fail; \
  69   lb t1, (offset + size)(base); \
  70   beqz t1, fail; \
  71   lb t1, (offset + 0)(base); \
  72   bnez t1, fail; \
  73   lb t1, (offset + size - 1)(base); \
  74   bnez t1, fail; \
  75 1:
  76
  77   MISALIGNED_STORE_TEST(22,  sh,  s0, 1, 2)
  78   MISALIGNED_STORE_TEST(23,  sw,  s0, 5, 4)
  79   MISALIGNED_STORE_TEST(24,  sw,  s0, 10, 4)
  80   MISALIGNED_STORE_TEST(25,  sw,  s0, 15, 4)
  81
  82 #if __riscv_xlen == 64
  83   MISALIGNED_STORE_TEST(26, sd, s0, 25, 8)
  84   MISALIGNED_STORE_TEST(27, sd, s0, 34, 8)
  85   MISALIGNED_STORE_TEST(28, sd, s0, 43, 8)
  86   MISALIGNED_STORE_TEST(29, sd, s0, 52, 8)
  87   MISALIGNED_STORE_TEST(30, sd, s0, 61, 8)
  88   MISALIGNED_STORE_TEST(31, sd, s0, 70, 8)
  89   MISALIGNED_STORE_TEST(32, sd, s0, 79, 8)
  90 #endif
  91
  92   TEST_PASSFAIL
  93
  94   .align 3
  95 mtvec_handler:
  96   csrr t0, mcause
  97   bne t0, s1, fail
  98
  99   csrr t0, mbadaddr
 100   bne t0, t1, fail
 101
 102   lb t0, (t0)
 103   beqz t0, fail
 104
 105   csrw mepc, t2
 106   mret
 107
 108 RVTEST_CODE_END
 109
 110   .data
 111 RVTEST_DATA_BEGIN
 112
 113 data:
 114   .align 3
 115 .word 0xaabbccdd
 116 .word 0x66778899
 117 .word 0x22334455
 118 .word 0xeeffee11
 119 .fill 0xff, 1, 80
 120
 121
 122   TEST_DATA
 123
 124 RVTEST_DATA_END