isa/rv64si/csr.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # csr.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test CSRRx and CSRRxI instructions.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23   #undef SSTATUS_SPP
  24   #define SSTATUS_SPP MSTATUS_MPP
  25 #endif
  26
  27   # For RV64, make sure UXL encodes RV64.  (UXL does not exist for RV32.)
  28 #if __riscv_xlen == 64
  29   # If running in M mode, use mstatus.MPP to check existence of U mode.
  30   # Otherwise, if in S mode, then U mode must exist and we don't need to check.
  31 #ifdef __MACHINE_MODE
  32   li t0, MSTATUS_MPP
  33   csrc mstatus, t0
  34   csrr t1, mstatus
  35   and t0, t0, t1
  36   bnez t0, 1f
  37 #endif
  38   # If U mode is present, UXL should be 2 (XLEN = 64-bit)
  39   TEST_CASE(13, a0, SSTATUS_UXL & (SSTATUS_UXL << 1), csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
  40 #ifdef __MACHINE_MODE
  41   j 2f
  42 1:
  43   # If U mode is not present, UXL should be 0
  44   TEST_CASE(14, a0, 0, csrr a0, sstatus; li a1, SSTATUS_UXL; and a0, a0, a1)
  45 2:
  46 #endif
  47 #endif
  48
  49   csrwi sscratch, 3
  50   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
  51   TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
  52   TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
  53   TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
  54   TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
  55   TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
  56   TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
  57   TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
  58
  59 #ifdef __MACHINE_MODE
  60   # Is F extension present?
  61   csrr a0, misa
  62   andi a0, a0, (1 << ('F' - 'A'))
  63   beqz a0, 1f
  64   # If so, make sure FP stores have no effect when mstatus.FS is off.
  65   li a1, MSTATUS_FS
  66   csrs mstatus, a1
  67 #ifdef __riscv_flen
  68   fmv.s.x f0, x0
  69   csrc mstatus, a1
  70   la a1, fsw_data
  71   TEST_CASE(10, a0, 1, fsw f0, (a1); lw a0, (a1));
  72 #else
  73   # Fail if this test is compiled without F but executed on a core with F.
  74   TEST_CASE(10, zero, 1)
  75 #endif
  76 1:
  77
  78   # Figure out if 'U' is set in misa
  79   csrr a0, misa   # a0 = csr(misa)
  80   srli a0, a0, 20 # a0 = a0 >> 20
  81   andi a0, a0, 1  # a0 = a0 & 1
  82   beqz a0, finish # if no user mode, skip the rest of these checks
  83   la t0, user_mode_end
  84   srli t0, t0, PMP_SHIFT
  85   csrr t1, pmpcfg0
  86   csrw pmpaddr0, t0
  87   csrr t1, pmpaddr0
  88   bne t0, t1, fail
  89   li t0, (PMP_R | PMP_W | PMP_X)   # giving read, write and execute permissions
  90   or t0, t0, PMP_TOR  # setting mode to TOR
  91   li t1, 255
  92   csrrc t1, pmpcfg0, t1
  93   csrrs t1, pmpcfg0, t0
  94   csrr  t1, pmpcfg0
  95   andi  t1, t1, 255
  96   bne t0, t1, fail
  97 #endif /* __MACHINE_MODE */
  98
  99   # jump to user land
 100   li t0, SSTATUS_SPP
 101   csrc sstatus, t0
 102   la t0, 1f
 103   csrw sepc, t0
 104   sret
 105   1:
 106
 107   # Make sure writing the cycle counter causes an exception.
 108   # Don't run in supervisor, as we don't delegate illegal instruction traps.
 109 #ifdef __MACHINE_MODE
 110   TEST_CASE(11, a0, 255, li a0, 255; csrrw a0, cycle, x0);
 111 #endif
 112
 113   # Make sure reading status in user mode causes an exception.
 114   # Don't run in supervisor, as we don't delegate illegal instruction traps.
 115 #ifdef __MACHINE_MODE
 116   TEST_CASE(12, a0, 255, li a0, 255; csrr a0, sstatus)
 117 #else
 118   TEST_CASE(12, x0, 0, nop)
 119 #endif
 120   scall
 121 finish:
 122   RVTEST_PASS
 123
 124   .align 2
 125   .global user_mode_end
 126 user_mode_end:
 127   nop
 128
 129   # We should only fall through to this if scall failed.
 130   TEST_PASSFAIL
 131
 132   .align 2
 133   .global stvec_handler
 134 stvec_handler:
 135   # Trapping on tests 10-12 is good news.
 136   # Note that since the test didn't complete, TESTNUM is smaller by 1.
 137   li t0, 9
 138   bltu TESTNUM, t0, 1f
 139   li t0, 11
 140   bleu TESTNUM, t0, privileged
 141 1:
 142
 143   # catch RVTEST_PASS and kick it up to M-mode
 144   csrr t0, scause
 145   li t1, CAUSE_USER_ECALL
 146   bne t0, t1, fail
 147   RVTEST_PASS
 148
 149 privileged:
 150   # Make sure scause indicates a lack of privilege.
 151   csrr t0, scause
 152   li t1, CAUSE_ILLEGAL_INSTRUCTION
 153   bne t0, t1, fail
 154   # Return to user mode, but skip the trapping instruction.
 155   csrr t0, sepc
 156   addi t0, t0, 4
 157   csrw sepc, t0
 158   sret
 159
 160 RVTEST_CODE_END
 161
 162   .data
 163 RVTEST_DATA_BEGIN
 164
 165 fsw_data: .word 1
 166
 167 RVTEST_DATA_END