Reflect changes to ISA
[riscv-tests.git] / isa / rv64si / ipi.S
1 #*****************************************************************************
2 # ipi.S
3 #-----------------------------------------------------------------------------
4 #
5 # Test interprocessor interrupts.
6 #
7
8 #include "riscv_test.h"
9 #include "test_macros.h"
10
11 RVTEST_RV64S
12 RVTEST_CODE_BEGIN
13
14 # clear pending IPIs then enable interrupts
15 la a0, handler
16 mtpcr a0, evec
17 mtpcr x0, clear_ipi
18 mfpcr a0, status
19 li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
20 or a0, a0, a1
21 mtpcr a0, status
22
23 # wait for all cores to boot
24 la a0, coreid
25 li a1, 1
26 amoadd.w x0, a1, 0(a0)
27 lw a3, 4(x0)
28 1: lw a1, 0(a0)
29 blt a1, a3, 1b
30
31 # IPI dominoes
32 mfpcr a0, hartid
33 1: bnez a0, 1b
34 add a0, a0, 1
35 rem a0, a0, a3
36 mtpcr a0, send_ipi
37 1: b 1b
38
39 handler:
40 mfpcr a0, hartid
41 bnez a0, 2f
42 RVTEST_PASS
43
44 TEST_PASSFAIL
45
46 2: add a0, a0, 1
47 rem a0, a0, a3
48 mtpcr a0, send_ipi
49 1: b 1b
50
51 RVTEST_CODE_END
52
53 .data
54 RVTEST_DATA_BEGIN
55
56 TEST_DATA
57
58 coreid: .word 0
59 foo: .word 0
60
61 RVTEST_DATA_END