isa/rv64si/ma_fetch.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_fetch.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned fetch trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64S
  14 RVTEST_CODE_BEGIN
  15
  16 #ifdef __MACHINE_MODE
  17   #define sscratch mscratch
  18   #define sstatus mstatus
  19   #define scause mcause
  20   #define sepc mepc
  21   #define sret mret
  22   #define stvec_handler mtvec_handler
  23 #endif
  24
  25   .option norvc
  26
  27   # Without RVC, the jalr should trap, and the handler will skip ahead.
  28   # With RVC, the jalr should not trap, and "j fail" should get skipped.
  29   li TESTNUM, 2
  30   li t1, 0
  31   la t0, 1f
  32   jalr t1, t0, 2
  33 1:
  34   .option rvc
  35   c.j 1f
  36   c.j 2f
  37   .option norvc
  38 1:
  39   j fail
  40 2:
  41
  42   // This test should pass, since JALR ignores the target LSB
  43   li TESTNUM, 3
  44   la t0, 1f
  45   jalr t1, t0, 1
  46 1:
  47   j 1f
  48   j fail
  49 1:
  50
  51   li TESTNUM, 4
  52   li t1, 0
  53   la t0, 1f
  54   jalr t1, t0, 3
  55 1:
  56   .option rvc
  57   c.j 1f
  58   c.j 2f
  59   .option norvc
  60 1:
  61   j fail
  62 2:
  63
  64   # Like test 2, but with jal instead of jalr.
  65   li TESTNUM, 5
  66   li t1, 0
  67   la t0, 1f
  68   jal t1, 2f
  69 1:
  70   .option rvc
  71   c.j 1f
  72 2:
  73   c.j 2f
  74   .option norvc
  75 1:
  76   j fail
  77 2:
  78
  79   # Like test 2, but with a taken branch instead of jalr.
  80   li TESTNUM, 6
  81   li t1, 0
  82   la t0, 1f
  83   beqz x0, 2f
  84 1:
  85   .option rvc
  86   c.j 1f
  87 2:
  88   c.j 2f
  89   .option norvc
  90 1:
  91   j fail
  92 2:
  93
  94   # Not-taken branches should not trap, even without RVC.
  95   li TESTNUM, 7
  96   bnez x0, 1f
  97   j 2f
  98   .option rvc
  99   c.j 1f
 100 1:
 101   c.j 1f
 102   .option norvc
 103 1:
 104   j fail
 105 2:
 106
 107   j pass
 108
 109   TEST_PASSFAIL
 110
 111   .align 2
 112 stvec_handler:
 113   # tests 2, 4, 5, and 6 should trap
 114   li a0, 2
 115   beq TESTNUM, a0, 1f
 116   li a0, 4
 117   beq TESTNUM, a0, 1f
 118   li a0, 5
 119   beq TESTNUM, a0, 1f
 120   li a0, 6
 121   beq TESTNUM, a0, 1f
 122   j fail
 123 1:
 124
 125   # verify that return address was not written
 126   bnez t1, fail
 127
 128   # verify trap cause
 129   li a1, CAUSE_MISALIGNED_FETCH
 130   csrr a0, scause
 131   bne a0, a1, fail
 132
 133   # verify that epc == &jalr (== t0 - 4)
 134   csrr a1, sepc
 135   addi t0, t0, -4
 136   bne t0, a1, fail
 137
 138   addi a1, a1, 12
 139   csrw sepc, a1
 140   sret
 141
 142 RVTEST_CODE_END
 143
 144   .data
 145 RVTEST_DATA_BEGIN
 146
 147   TEST_DATA
 148
 149 RVTEST_DATA_END