d5a2de7a0852ed52ad1c89ccdd115af17040569a
[riscv-tests.git] / isa / rv64si / sbreak.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # scall.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test syscall trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64S
14 RVTEST_CODE_BEGIN
15
16 #ifdef __MACHINE_MODE
17 #define sscratch mscratch
18 #define sstatus mstatus
19 #define scause mcause
20 #define sepc mepc
21 #define sret mret
22 #define stvec_handler mtvec_handler
23 #endif
24
25 li TESTNUM, 2
26
27 sbreak
28 j fail
29
30 TEST_PASSFAIL
31
32 .align 2
33 .global stvec_handler
34 stvec_handler:
35 li t1, CAUSE_BREAKPOINT
36 csrr t0, scause
37 bne t0, t1, fail
38 j pass
39
40 RVTEST_CODE_END
41
42 .data
43 RVTEST_DATA_BEGIN
44
45 TEST_DATA
46
47 RVTEST_DATA_END