Add another FP recoding test case
[riscv-tests.git] / isa / rv64sv / illegal_cfg_nfpr.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # illegal_tvec_cmd.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test illegal tvec command trap.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64SV
14 RVTEST_CODE_BEGIN
15
16 li a0,33
17 slli a0,a0,6
18 vsetcfg a0
19
20 vtcode2:
21 add x2,x2,x3
22 stop
23
24 stvec_handler:
25 vxcptkill
26
27 li TESTNUM,2
28
29 # check cause
30 csrr a3, scause
31 li a4,HWACHA_CAUSE_ILLEGAL_CFG
32 bne a3,a4,fail
33
34 # check vec irq aux
35 csrr a3, sbadaddr
36 li a4, 1
37 bne a3,a4,fail
38
39 # make sure vector unit has cleared out
40 vsetcfg 32,0
41 li a3,4
42 vsetvl a3,a3
43
44 la a3,src1
45 la a4,src2
46 vld vx2,a3
47 vld vx3,a4
48 lui a0,%hi(vtcode2)
49 vf %lo(vtcode2)(a0)
50 la a5,dest
51 vsd vx2,a5
52 fence
53
54 ld a1,0(a5)
55 li a2,5
56 li TESTNUM,2
57 bne a1,a2,fail
58 ld a1,8(a5)
59 li TESTNUM,3
60 bne a1,a2,fail
61 ld a1,16(a5)
62 li TESTNUM,4
63 bne a1,a2,fail
64 ld a1,24(a5)
65 li TESTNUM,5
66 bne a1,a2,fail
67
68 TEST_PASSFAIL
69
70 RVTEST_CODE_END
71
72 .data
73 RVTEST_DATA_BEGIN
74
75 TEST_DATA
76
77 src1:
78 .dword 1
79 .dword 2
80 .dword 3
81 .dword 4
82 src2:
83 .dword 4
84 .dword 3
85 .dword 2
86 .dword 1
87 dest:
88 .dword 0xdeadbeefcafebabe
89 .dword 0xdeadbeefcafebabe
90 .dword 0xdeadbeefcafebabe
91 .dword 0xdeadbeefcafebabe
92
93 RVTEST_DATA_END