isa/rv64sv/ma_vld.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # ma_vld.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test misaligned vector ld trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   vsetcfg 32,0
  17   li a3,4
  18   vsetvl a3,a3
  19
  20   la a3, dest+1
  21   vld vx2,a3
  22   vld vx3,a4
  23   lui a0,%hi(vtcode1)
  24   vf %lo(vtcode1)(a0)
  25   fence
  26
  27 vtcode1:
  28   add x2,x2,x3
  29   stop
  30
  31 vtcode2:
  32   add x2,x2,x3
  33   stop
  34
  35 stvec_handler:
  36   vxcptkill
  37
  38   li TESTNUM,2
  39
  40   # check cause
  41   csrr a3, scause
  42   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
  43   bne a3,a4,fail
  44
  45   # check vec irq aux
  46   csrr a3, sbadaddr
  47   la a4,dest+1
  48   bne a3,a4,fail
  49
  50   # make sure vector unit has cleared out
  51   vsetcfg 32,0
  52   li a3,4
  53   vsetvl a3,a3
  54
  55   la a3,src1
  56   la a4,src2
  57   vld vx2,a3
  58   vld vx3,a4
  59   lui a0,%hi(vtcode2)
  60   vf %lo(vtcode2)(a0)
  61   la a5,dest
  62   vsd vx2,a5
  63   fence
  64
  65   ld a1,0(a5)
  66   li a2,5
  67   li TESTNUM,2
  68   bne a1,a2,fail
  69   ld a1,8(a5)
  70   li TESTNUM,3
  71   bne a1,a2,fail
  72   ld a1,16(a5)
  73   li TESTNUM,4
  74   bne a1,a2,fail
  75   ld a1,24(a5)
  76   li TESTNUM,5
  77   bne a1,a2,fail
  78
  79   TEST_PASSFAIL
  80
  81 RVTEST_CODE_END
  82
  83   .data
  84 RVTEST_DATA_BEGIN
  85
  86   TEST_DATA
  87
  88 src1:
  89   .dword 1
  90   .dword 2
  91   .dword 3
  92   .dword 4
  93 src2:
  94   .dword 4
  95   .dword 3
  96   .dword 2
  97   .dword 1
  98 dest:
  99   .dword 0xdeadbeefcafebabe
 100   .dword 0xdeadbeefcafebabe
 101   .dword 0xdeadbeefcafebabe
 102   .dword 0xdeadbeefcafebabe
 103
 104 RVTEST_DATA_END