isa/rv64sv/privileged_inst.S

   1 # See LICENSE for license details.
   2
   3 #*****************************************************************************
   4 # illegal_tvec_cmd.S
   5 #-----------------------------------------------------------------------------
   6 #
   7 # Test illegal tvec command trap.
   8 #
   9
  10 #include "riscv_test.h"
  11 #include "test_macros.h"
  12
  13 RVTEST_RV64SV
  14 RVTEST_CODE_BEGIN
  15
  16   li a3, SSTATUS_PS
  17   csrc sstatus, a3
  18   la t0, 1f
  19   csrw sepc, t0
  20   sret
  21 1:
  22
  23 privileged_inst:
  24   vxcptcause a3 # privileged inst
  25
  26 vtcode2:
  27   add x2,x2,x3
  28   stop
  29
  30 stvec_handler:
  31   vxcptkill
  32
  33   li TESTNUM,2
  34
  35   # check cause
  36   csrr a3, scause
  37   li a4,HWACHA_CAUSE_PRIVILEGED_INSTRUCTION
  38   bne a3,a4,fail
  39
  40   # check vec irq aux
  41   csrr a3, sbadaddr
  42   la a4, privileged_inst
  43   lw a5, 0(a4)
  44   bne a3,a5,fail
  45
  46   # make sure vector unit has cleared out
  47   vsetcfg 32,0
  48   li a3,4
  49   vsetvl a3,a3
  50
  51   la a3,src1
  52   la a4,src2
  53   vld vx2,a3
  54   vld vx3,a4
  55   lui a0,%hi(vtcode2)
  56   vf %lo(vtcode2)(a0)
  57   la a5,dest
  58   vsd vx2,a5
  59   fence
  60
  61   ld a1,0(a5)
  62   li a2,5
  63   li TESTNUM,2
  64   bne a1,a2,fail
  65   ld a1,8(a5)
  66   li TESTNUM,3
  67   bne a1,a2,fail
  68   ld a1,16(a5)
  69   li TESTNUM,4
  70   bne a1,a2,fail
  71   ld a1,24(a5)
  72   li TESTNUM,5
  73   bne a1,a2,fail
  74
  75   TEST_PASSFAIL
  76
  77 RVTEST_CODE_END
  78
  79   .data
  80 RVTEST_DATA_BEGIN
  81
  82   TEST_DATA
  83
  84 src1:
  85   .dword 1
  86   .dword 2
  87   .dword 3
  88   .dword 4
  89 src2:
  90   .dword 4
  91   .dword 3
  92   .dword 2
  93   .dword 1
  94 dest:
  95   .dword 0xdeadbeefcafebabe
  96   .dword 0xdeadbeefcafebabe
  97   .dword 0xdeadbeefcafebabe
  98   .dword 0xdeadbeefcafebabe
  99
 100 RVTEST_DATA_END