isa/rv64uc/sv_c_mv.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6
   7 # SV test: vector-vector add different rd and rs1
   8 #
   9 # sets up x6 and x7 with data, sets VL to 2, and carries out
  10 # an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         .option norvc
  16
  17         SV_LD_DATA( x5, testdata+0 , 0)
  18         SV_LD_DATA( x6, testdata+8, 0)
  19         SV_LD_DATA( x7, testdata+16, 0)
  20
  21         li          x2, 0 # deliberately set x3 to 0 (target of add)
  22         li          x3, 0 # deliberately set x4 to 0
  23         li          x4, 0 # deliberately set x4 to 0
  24
  25         SET_SV_MVL(3)
  26         SET_SV_2CSRS( SV_REG_CSR(1, 2, 0, 2, 1, 0),
  27                       SV_REG_CSR(1, 5, 0, 5, 1, 0) )
  28         SET_SV_VL(3)
  29
  30         .option rvc
  31         c.mv    x2, x5
  32         .option norvc
  33
  34         SET_SV_VL(0)
  35         CLR_SV_CSRS()
  36         SET_SV_MVL(0)
  37
  38         TEST_SV_IMM(x2, 1001) # should not be modified
  39         TEST_SV_IMM(x3, 41)
  40         TEST_SV_IMM(x4, 42)
  41
  42         RVTEST_PASS           # Signal success.
  43 fail:
  44         RVTEST_FAIL
  45 RVTEST_CODE_END     # End of test code.
  46
  47 # Input data section.
  48 # This section is optional, and this data is NOT saved in the output.
  49 .data
  50         .align 3
  51 testdata:
  52         .dword 1001
  53         .dword 41
  54         .dword 42
  55
  56 # Output data section.
  57 RVTEST_DATA_BEGIN   # Start of test output data region.
  58         .align 3
  59 result:
  60         .dword -1
  61         .dword -1
  62         .dword -1
  63 RVTEST_DATA_END     # End of test output data region.
  64