add some twin-predication zeroing unit tests on c.mv
[riscv-tests.git] / isa / rv64uc / sv_c_mv_predication.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6
7 #define SV_PRED_C_MV_TEST( pred1, pred2, zero1, zero2, \
8 expect1, expect2, expect3 ) \
9 \
10 SV_LD_DATA( x6, testdata+0 , 0); \
11 SV_LD_DATA( x7, testdata+8, 0); \
12 SV_LD_DATA( x8, testdata+16, 0); \
13 \
14 li x3, 2; \
15 li x4, 3; \
16 li x5, 4; \
17 li a3, pred1; \
18 li a4, pred2; \
19 \
20 SET_SV_MVL(3); \
21 SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1), \
22 SV_REG_CSR(1, 6, 0, 6, 1) ); \
23 SET_SV_2PREDCSRS( \
24 SV_PRED_CSR(1, 3, zero1, 0, 13, 0), \
25 SV_PRED_CSR(1, 6, zero2, 0, 14, 0) );\
26 SET_SV_VL(3); \
27 \
28 .option rvc; \
29 c.mv x3, x6; \
30 .option norvc; \
31 \
32 SET_SV_VL(1); \
33 CLR_SV_CSRS(); \
34 SET_SV_MVL(1); \
35 \
36 TEST_SV_IMM(x3, expect1); \
37 TEST_SV_IMM(x4, expect2); \
38 TEST_SV_IMM(x5, expect3);
39
40 # SV test: vector-vector add different rd and rs1
41 #
42 # sets up x6 and x7 with data, sets VL to 2, and carries out
43 # an "x3 = 1 + x6". which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
44
45 # Test code region.
46 RVTEST_CODE_BEGIN # Start of test code.
47
48 .option norvc
49
50 SV_PRED_C_MV_TEST( 0x7, 0x7, 0, 0, 1001, 41, 42 )
51 SV_PRED_C_MV_TEST( 0x3, 0x7, 0, 0, 1001, 41, 4 )
52 SV_PRED_C_MV_TEST( 0x1, 0x7, 0, 0, 1001, 3, 4 )
53
54 SV_PRED_C_MV_TEST( 0x6, 0x7, 0, 0, 2, 1001, 41 )
55 SV_PRED_C_MV_TEST( 0x6, 0x3, 0, 0, 2, 1001, 41 )
56 SV_PRED_C_MV_TEST( 0x6, 0x1, 0, 0, 2, 1001, 4 )
57 SV_PRED_C_MV_TEST( 0x6, 0x6, 0, 0, 2, 41, 42 )
58
59 SV_PRED_C_MV_TEST( 0x5, 0x6, 0, 0, 41, 3, 42 )
60
61 SV_PRED_C_MV_TEST( 0x1, 0x1, 0, 0, 1001, 3, 4 )
62 SV_PRED_C_MV_TEST( 0x2, 0x1, 0, 0, 2, 1001, 4 )
63 SV_PRED_C_MV_TEST( 0x4, 0x1, 0, 0, 2, 3, 1001 )
64
65 SV_PRED_C_MV_TEST( 0x1, 0x1, 0, 0, 1001, 3, 4 )
66 SV_PRED_C_MV_TEST( 0x1, 0x2, 0, 0, 41, 3, 4 )
67 SV_PRED_C_MV_TEST( 0x1, 0x4, 0, 0, 42, 3, 4 )
68
69 # test zeroing with predication
70 SV_PRED_C_MV_TEST( 0x1, 0x1, 1, 1, 1001, 0, 0 )
71 SV_PRED_C_MV_TEST( 0x2, 0x3, 1, 1, 0, 41, 0 )
72 SV_PRED_C_MV_TEST( 0x5, 0x5, 1, 1, 1001, 0, 42 )
73 SV_PRED_C_MV_TEST( 0x1, 0x1, 1, 0, 1001, 3, 4 )
74 SV_PRED_C_MV_TEST( 0x2, 0x3, 1, 0, 0, 41, 4 )
75 SV_PRED_C_MV_TEST( 0x5, 0x5, 1, 0, 1001, 0, 4 )
76
77 RVTEST_PASS # Signal success.
78 fail:
79 RVTEST_FAIL
80 RVTEST_CODE_END # End of test code.
81
82 # Input data section.
83 # This section is optional, and this data is NOT saved in the output.
84 .data
85 .align 3
86 testdata:
87 .dword 1001
88 .dword 41
89 .dword 42
90
91 # Output data section.
92 RVTEST_DATA_BEGIN # Start of test output data region.
93 .align 3
94 result:
95 .dword -1
96 .dword -1
97 .dword -1
98 RVTEST_DATA_END # End of test output data region.
99