Rv32ud tests (#108)
[riscv-tests.git] / isa / rv64ud / fcmp.S
1 # See LICENSE for license details.
2
3 #*****************************************************************************
4 # fcmp.S
5 #-----------------------------------------------------------------------------
6 #
7 # Test f{eq|lt|le}.d instructions.
8 #
9
10 #include "riscv_test.h"
11 #include "test_macros.h"
12
13 RVTEST_RV64UF
14 RVTEST_CODE_BEGIN
15
16 #-------------------------------------------------------------
17 # Arithmetic tests
18 #-------------------------------------------------------------
19
20 #if __riscv_xlen == 32
21 # Replace the function with the 32-bit variant defined in test_macros.h
22 #undef TEST_FP_CMP_OP_D
23 #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32
24 #endif
25
26 TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36)
27 TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36)
28 TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36)
29
30 TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36)
31 TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36)
32 TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36)
33
34 # Only sNaN should signal invalid for feq.
35 TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0)
36 TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN)
37 TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0)
38
39 # qNaN should signal invalid for fle/flt.
40 TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0)
41 TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN)
42 TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0)
43 TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0)
44 TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN)
45 TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0)
46
47 TEST_PASSFAIL
48
49 RVTEST_CODE_END
50
51 .data
52 RVTEST_DATA_BEGIN
53
54 TEST_DATA
55
56 RVTEST_DATA_END