isa/rv64uf/sv_fadd_elwidth.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64UF
   5
   6 #define SV_ELWIDTH_TEST( vl, wid1, wid2, wid3, tdata, ans ) \
   7                                                                 \
   8         SV_FLW_DATA( f4, ( tdata + 0) , 0) ;                      \
   9         SV_FLW_DATA( f5, ( tdata + 4), 0)  ;                      \
  10         SV_FLW_DATA( f6, ( tdata + 8), 0)  ;                      \
  11         SV_FLW_DATA( f7, ( tdata + 12), 0) ;                      \
  12                                                                 \
  13         SET_SV_MVL( vl )                      ;                    \
  14         SET_SV_3CSRS( SV_REG_CSR(0, 2, wid1, 2, 1),                \
  15                       SV_REG_CSR(0, 4, wid2, 4, 1),                \
  16                       SV_REG_CSR(0, 6, wid3, 6, 1) ) ;             \
  17         SET_SV_VL( vl ) ;                                          \
  18                                                                 \
  19         fadd.s f2, f4, f6;                                      \
  20                                                                 \
  21         CLR_SV_CSRS() ;                                         \
  22         SET_SV_VL(1) ;                                          \
  23         SET_SV_MVL(1) ;                                         \
  24                                                                 \
  25         TEST_SV_FW(0, f2, ans+0, 0) ;                        \
  26         TEST_SV_FW(0, f3, ans+4, 0)
  27
  28 # SV test: vector-vector fadd
  29 #
  30 # sets up x3 and x4 with data, sets VL to 2, and carries out
  31 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  32
  33 # Test code region.
  34 RVTEST_CODE_BEGIN   # Start of test code.
  35
  36         SV_ELWIDTH_TEST( 2, 2, 0, 0, testdata, answer );
  37         SV_ELWIDTH_TEST( 2, 2, 2, 0, testdata2, answer2 );
  38
  39         RVTEST_PASS           # Signal success.
  40 fail:
  41         RVTEST_FAIL
  42 RVTEST_CODE_END     # End of test code.
  43
  44 # Input data section.
  45 # This section is optional, and this data is NOT saved in the output.
  46 .data
  47         .align 3
  48 testdata:
  49         .float 41.0
  50         .float 42.0
  51         .float 1.0
  52         .float 2.0
  53 answer:
  54         .word 0x51805140 # 44 fp16 42 fp16, tested as-is, even if it goes to fp
  55         .word 0x0        # before going to int for comparison (TEST_SV_FW)
  56
  57
  58 testdata2:
  59         .word 0x51405120   # 42 fp16 41 fp16
  60         .word 0xffff5140   # 42 fp16
  61         .float 1.0
  62         .float 2.0
  63 answer2:
  64         .word 0x51805140
  65         .word 0x0
  66 # Output data section.
  67 RVTEST_DATA_BEGIN   # Start of test output data region.
  68         .align 3
  69 result:
  70         .dword -1
  71         .dword -1
  72         .dword -1
  73 RVTEST_DATA_END     # End of test output data region.
  74