isa/rv64uf/sv_fadd_elwidth.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64UF
   5
   6
   7 # SV test: vector-vector fadd
   8 #
   9 # sets up x3 and x4 with data, sets VL to 2, and carries out
  10 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         SV_FLW_DATA( f4, testdata+0 , 0)
  16         SV_FLW_DATA( f5, testdata+4, 0)
  17         SV_FLW_DATA( f6, testdata+8, 0)
  18         SV_FLW_DATA( f7, testdata+12, 0)
  19
  20         SET_SV_MVL(2)
  21         SET_SV_3CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
  22                       SV_REG_CSR(0, 4, 0, 4, 1),
  23                       SV_REG_CSR(0, 6, 0, 6, 1) )
  24         SET_SV_VL(2)
  25
  26         fadd.s f2, f4, f6;
  27
  28         CLR_SV_CSRS()
  29         SET_SV_VL(1)
  30         SET_SV_MVL(1)
  31
  32         TEST_SV_FW(0, f2, answer+0, 0)
  33         TEST_SV_FW(0, f3, answer+4, 0)
  34
  35         RVTEST_PASS           # Signal success.
  36 fail:
  37         RVTEST_FAIL
  38 RVTEST_CODE_END     # End of test code.
  39
  40 # Input data section.
  41 # This section is optional, and this data is NOT saved in the output.
  42 .data
  43         .align 3
  44 testdata:
  45         .float 41.0
  46         .float 42.0
  47         .float 1.0
  48         .float 2.0
  49 answer:
  50         #.word 0x5140
  51         #.word 0x5100
  52         .float 42.0
  53         .float 44.0
  54
  55 # Output data section.
  56 RVTEST_DATA_BEGIN   # Start of test output data region.
  57         .align 3
  58 result:
  59         .dword -1
  60         .dword -1
  61         .dword -1
  62 RVTEST_DATA_END     # End of test output data region.
  63