20cbeeba4739beb67cba125ac6d1b4d069053040
[riscv-tests.git] / isa / rv64uf / sv_fld_elwidth.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64UF # Define TVM used by program.
5
6 #define SV_ELWIDTH_TESTW( inst, vl, elwidth, wid1, wid2, \
7 testdata, ans ) \
8 \
9 la x12, testdata ; \
10 la x13, (testdata+elwidth); \
11 la x14, (testdata+elwidth*2); \
12 la x15, (testdata+elwidth*3); \
13 la x16, (testdata+elwidth*4); \
14 la x17, (testdata+elwidth*5); \
15 \
16 li x1, 0xa5a5a5a5a5a5a5a5; \
17 fmv.d.x f28, x1; \
18 fmv.d.x f29, x1; \
19 fmv.d.x f30, x1; \
20 \
21 SET_SV_MVL( vl); \
22 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1), \
23 SV_REG_CSR( 0, 28, wid2, 28, 1)); \
24 SET_SV_VL( vl ); \
25 \
26 inst f28, 0(x12); \
27 \
28 CLR_SV_CSRS(); \
29 SET_SV_VL( 1); \
30 SET_SV_MVL( 1); \
31 \
32 TEST_SV_FW(0, f28, ans, 0); \
33 TEST_SV_FW(0, f29, ans, 4); \
34 TEST_SV_FW(0, f30, ans, 8);
35
36 #define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
37 testdata, ans ) \
38 \
39 la x12, testdata ; \
40 la x13, (testdata+elwidth); \
41 la x14, (testdata+elwidth*2); \
42 la x15, (testdata+elwidth*3); \
43 la x16, (testdata+elwidth*4); \
44 la x17, (testdata+elwidth*5); \
45 \
46 li x1, 0xa5a5a5a5a5a5a5a5; \
47 fmv.d.x f28, x1; \
48 fmv.d.x f29, x1; \
49 fmv.d.x f30, x1; \
50 \
51 SET_SV_MVL( vl); \
52 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1), \
53 SV_REG_CSR( 0, 28, wid2, 28, 1)); \
54 SET_SV_VL( vl ); \
55 \
56 inst f28, 0(x12); \
57 \
58 CLR_SV_CSRS(); \
59 SET_SV_VL( 1); \
60 SET_SV_MVL( 1); \
61 \
62 TEST_SV_FD(0, f28, ans, 0); \
63 TEST_SV_FD(0, f29, ans, 8); \
64 TEST_SV_FD(0, f30, ans, 16);
65
66 # SV test: vector-vector add
67 #
68 # sets up x3 and x4 with data, sets VL to 2, and carries out
69 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
70
71 # Test code region.
72 RVTEST_CODE_BEGIN # Start of test code.
73
74 SV_ELWIDTH_TEST( fld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
75 SV_ELWIDTH_TEST( fld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer2 )
76 SV_ELWIDTH_TEST( fld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3)
77 SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
78 SV_ELWIDTH_TEST( fld , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
79
80 SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
81 SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_16BIT, SV_W_DFLT, testdata3, answer8)
82 SV_ELWIDTH_TESTW(flw , 4, 4, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
83 /*
84 XXX: causes unexpected results, possibly memory corruption?
85 SV_ELWIDTH_TESTW(flw , 5, 4, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
86 */
87 /*
88 SV_ELWIDTH_TESTW(flw , 2, 4, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
89 SV_ELWIDTH_TESTW(flw , 6, 4, SV_W_DFLT, SV_W_16BIT, testdata6, answer5)
90 */
91 RVTEST_PASS # Signal success.
92 fail:
93 RVTEST_FAIL
94 RVTEST_CODE_END # End of test code.
95
96 # Input data section.
97 # This section is optional, and this data is NOT saved in the output.
98 .data
99 .align 3
100 testdata1:
101 .dword 0x8979695949392919
102 .dword 0x8777675747372717
103 .dword 0x8676665646362616
104 .dword 0x8272625242322212
105 .dword 0x8171615141312111
106 .dword 0x8373635343332313
107
108 .align 3
109 answer1:
110 .dword 0x8979695949392919
111 .dword 0x8777675747372717
112 .dword 0xa5a5a5a5a5a5a5a5
113
114 .align 3
115 answer2:
116
117 .dword 0x8979695949392919
118 .dword 0x8777675747372717
119 .dword 0x8676665646362616
120
121 .align 3
122 testdata3:
123 .dword 0x63d03c0051805140
124 .dword 0x000000000000E480
125 .dword 0x8676665646362616
126 .dword 0x8272625242322212
127 .dword 0x8171615141312111
128 .dword 0x8373635343332313
129
130 .align 3
131 answer3:
132
133 .double 42.0
134 .double 44.0
135 .double 1.0
136
137 .align 3
138 answer4:
139
140 .float 42.0
141 .float 44.0
142 .float 1.0
143 .float 1000.0
144 .float -1152.0
145 .word 0xa5a5a5a5
146
147 .align 3
148 testdata4:
149
150 .float 42.0
151 .float 44.0
152 .float 1.0
153 .float 1000.0
154 .float -1152.0
155 .float -82.0
156 .float 0x0
157 .word 0xa5a5a5a5
158
159 .align 3
160 answer5:
161
162 .short 0x5140 # 42 fp16
163 .short 0x5180 # 44 fp16
164 .short 0x3c00 # 1.0 fp16
165 .short 0x63d0 # 1000.0 fp16
166 .short 0xe480 # -1152.0 fp16
167 .short 0xd520 # -82 fp16
168 .short 0xa5a5
169 .short 0xa5a5
170 .dword 0xa5a5a5a5a5a5a5a5
171
172 .align 3
173 testdata6:
174
175 .float 42.0
176 .float 44.0
177 .float 1.0
178 .float 1000.0
179 .float -1152.0
180 .float -82.0
181 .dword 0x0
182 .dword 0x0
183 .dword 0x0
184 .dword 0x0
185 .dword 0x0
186 .dword 0x0
187 .dword 0x0
188
189 answer7:
190 .dword 0xa5a5a5a549392919
191 .dword 0xa5a5a5a589796959
192 .dword 0x8777675747372717
193 .dword 0xa5a5a5a5a5a5a5a5
194
195 .align 3
196
197 answer8:
198
199 .float 42.0
200 .float 44.0
201 .float 1.0
202
203 .align 3
204 # Output data section.
205 RVTEST_DATA_BEGIN # Start of test output data region.
206 .align 3
207 result:
208 .dword -1
209 .dword -1
210 .dword -1
211 RVTEST_DATA_END # End of test output data region.
212