isa/rv64uf/sv_fld_elwidth.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64UF        # Define TVM used by program.
   5
   6 #define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
   7                          testdata, ans ) \
   8                                                         \
   9         la x12, testdata ;                              \
  10         la x13, (testdata+elwidth);                              \
  11         la x14, (testdata+elwidth*2);                              \
  12         la x15, (testdata+elwidth*3);                              \
  13         la x16, (testdata+elwidth*4);                              \
  14         la x17, (testdata+elwidth*5);                              \
  15                                                         \
  16         li x1, 0xa5a5a5a5a5a5a5a5;                                      \
  17         fmv.d.x f28, x1;                                   \
  18         fmv.d.x f29, x1;                                   \
  19         fmv.d.x f30, x1;                                   \
  20                                                         \
  21         SET_SV_MVL( vl);                                  \
  22         SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1),        \
  23                       SV_REG_CSR( 0, 28, wid2, 28, 1));       \
  24         SET_SV_VL( vl );                                   \
  25                                                         \
  26         inst   f28, 0(x12);                              \
  27                                                         \
  28         CLR_SV_CSRS();                                  \
  29         SET_SV_VL( 1);                                   \
  30         SET_SV_MVL( 1);                                  \
  31                                                         \
  32         TEST_SV_FD(0, f28, ans, 0);                    \
  33         TEST_SV_FD(0, f29, ans, 8);                    \
  34         TEST_SV_FD(0, f30, ans, 16);
  35
  36 # SV test: vector-vector add
  37 #
  38 # sets up x3 and x4 with data, sets VL to 2, and carries out
  39 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  40
  41 # Test code region.
  42 RVTEST_CODE_BEGIN   # Start of test code.
  43
  44         SV_ELWIDTH_TEST( fld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
  45         SV_ELWIDTH_TEST( fld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer2 )
  46         SV_ELWIDTH_TEST( fld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3)
  47         SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
  48         SV_ELWIDTH_TEST( fld , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
  49 /*
  50         SV_ELWIDTH_TEST(  ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1,
  51                 0x6757271769592919,  0xa5a5a5a5a5a52616,  0xa5a5a5a5a5a5a5a5 )
  52         SV_ELWIDTH_TEST(  ld , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1,
  53                 0xa557371779593919,  0xa5a5a5a5a5a5a5a5,  0xa5a5a5a5a5a5a5a5 )
  54         SV_ELWIDTH_TEST(  ld , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1,
  55                 0x0049003900290019,  0xff89007900690059,  0xa5a5003700270017 )
  56 */
  57         RVTEST_PASS           # Signal success.
  58 fail:
  59         RVTEST_FAIL
  60 RVTEST_CODE_END     # End of test code.
  61
  62 # Input data section.
  63 # This section is optional, and this data is NOT saved in the output.
  64 .data
  65         .align 3
  66 testdata1:
  67         .dword 0x8979695949392919
  68         .dword 0x8777675747372717
  69         .dword 0x8676665646362616
  70         .dword 0x8272625242322212
  71         .dword 0x8171615141312111
  72         .dword 0x8373635343332313
  73
  74 answer1:
  75         .dword 0x8979695949392919
  76         .dword 0x8777675747372717
  77         .dword 0xa5a5a5a5a5a5a5a5
  78
  79 answer2:
  80
  81         .dword 0x8979695949392919
  82         .dword 0x8777675747372717
  83         .dword 0x8676665646362616
  84
  85 testdata3:
  86         .dword 0x63d03c0051805140
  87         .dword 0x000000000000E480
  88         .dword 0x8676665646362616
  89         .dword 0x8272625242322212
  90         .dword 0x8171615141312111
  91         .dword 0x8373635343332313
  92
  93 answer3:
  94
  95         .double 42.0
  96         .double 44.0
  97         .double 1.0
  98
  99 answer4:
 100
 101         .float 42.0
 102         .float 44.0
 103         .float 1.0
 104         .float 1000.0
 105         .float -1152.0
 106         .word 0xa5a5a5a5
 107
 108 testdata4:
 109
 110         .float 42.0
 111         .float 44.0
 112         .float 1.0
 113         .float 1000.0
 114         .float -1152.0
 115         .float -82.0
 116         .word 0xa5a5a5a5
 117
 118 answer5:
 119
 120         .short 0x5140 # 42 fp16
 121         .short 0x5180 # 44 fp16
 122         .short 0x3c00 # 1.0 fp16
 123         .short 0x63d0 # 1000.0 fp16
 124         .short 0xe480 # -1152.0 fp16
 125         .short 0xd520 # -82 fp16
 126         .short 0xa5a5
 127         .short 0xa5a5
 128         .dword 0xa5a5a5a5a5a5a5a5
 129
 130 # Output data section.
 131 RVTEST_DATA_BEGIN   # Start of test output data region.
 132         .align 3
 133 result:
 134         .dword -1
 135         .dword -1
 136         .dword -1
 137 RVTEST_DATA_END     # End of test output data region.
 138