add alignment on testdata
[riscv-tests.git] / isa / rv64uf / sv_fld_elwidth.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64UF # Define TVM used by program.
5
6 #define SV_ELWIDTH_TESTW( inst, vl, elwidth, wid1, wid2, \
7 testdata, ans ) \
8 \
9 la x12, testdata ; \
10 la x13, (testdata+elwidth); \
11 la x14, (testdata+elwidth*2); \
12 la x15, (testdata+elwidth*3); \
13 la x16, (testdata+elwidth*4); \
14 la x17, (testdata+elwidth*5); \
15 \
16 li x1, 0xa5a5a5a5a5a5a5a5; \
17 fmv.d.x f28, x1; \
18 fmv.d.x f29, x1; \
19 fmv.d.x f30, x1; \
20 \
21 SET_SV_MVL( vl); \
22 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1), \
23 SV_REG_CSR( 0, 28, wid2, 28, 1)); \
24 SET_SV_VL( vl ); \
25 \
26 inst f28, 0(x12); \
27 \
28 CLR_SV_CSRS(); \
29 SET_SV_VL( 1); \
30 SET_SV_MVL( 1); \
31 \
32 TEST_SV_FW(0, f28, ans, 0); \
33 TEST_SV_FW(0, f29, ans, 4); \
34 TEST_SV_FW(0, f30, ans, 8);
35
36 #define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \
37 testdata, ans ) \
38 \
39 la x12, testdata ; \
40 la x13, (testdata+elwidth); \
41 la x14, (testdata+elwidth*2); \
42 la x15, (testdata+elwidth*3); \
43 la x16, (testdata+elwidth*4); \
44 la x17, (testdata+elwidth*5); \
45 \
46 li x1, 0xa5a5a5a5a5a5a5a5; \
47 fmv.d.x f28, x1; \
48 fmv.d.x f29, x1; \
49 fmv.d.x f30, x1; \
50 \
51 SET_SV_MVL( vl); \
52 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 1), \
53 SV_REG_CSR( 0, 28, wid2, 28, 1)); \
54 SET_SV_VL( vl ); \
55 \
56 inst f28, 0(x12); \
57 \
58 CLR_SV_CSRS(); \
59 SET_SV_VL( 1); \
60 SET_SV_MVL( 1); \
61 \
62 TEST_SV_FD(0, f28, ans, 0); \
63 TEST_SV_FD(0, f29, ans, 8); \
64 TEST_SV_FD(0, f30, ans, 16);
65
66 # SV test: vector-vector add
67 #
68 # sets up x3 and x4 with data, sets VL to 2, and carries out
69 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
70
71 # Test code region.
72 RVTEST_CODE_BEGIN # Start of test code.
73
74 SV_ELWIDTH_TEST( fld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
75 SV_ELWIDTH_TEST( fld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer2 )
76 SV_ELWIDTH_TEST( fld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3)
77 SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
78 SV_ELWIDTH_TEST( fld , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
79
80 /*
81 SV_ELWIDTH_TESTW(flw , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 )
82 SV_ELWIDTH_TESTW(flw , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3)
83 SV_ELWIDTH_TESTW(flw , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4)
84 SV_ELWIDTH_TESTW(flw , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5)
85 SV_ELWIDTH_TESTW(flw , 6, 8, SV_W_DFLT, SV_W_16BIT, testdata6, answer5)
86
87 SV_ELWIDTH_TEST( ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1,
88 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 )
89 SV_ELWIDTH_TEST( ld , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1,
90 0xa557371779593919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 )
91 SV_ELWIDTH_TEST( ld , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1,
92 0x0049003900290019, 0xff89007900690059, 0xa5a5003700270017 )
93 */
94 RVTEST_PASS # Signal success.
95 fail:
96 RVTEST_FAIL
97 RVTEST_CODE_END # End of test code.
98
99 # Input data section.
100 # This section is optional, and this data is NOT saved in the output.
101 .data
102 .align 3
103 testdata1:
104 .dword 0x8979695949392919
105 .dword 0x8777675747372717
106 .dword 0x8676665646362616
107 .dword 0x8272625242322212
108 .dword 0x8171615141312111
109 .dword 0x8373635343332313
110
111 .align 3
112 answer1:
113 .dword 0x8979695949392919
114 .dword 0x8777675747372717
115 .dword 0xa5a5a5a5a5a5a5a5
116
117 .align 3
118 answer2:
119
120 .dword 0x8979695949392919
121 .dword 0x8777675747372717
122 .dword 0x8676665646362616
123
124 .align 3
125 testdata3:
126 .dword 0x63d03c0051805140
127 .dword 0x000000000000E480
128 .dword 0x8676665646362616
129 .dword 0x8272625242322212
130 .dword 0x8171615141312111
131 .dword 0x8373635343332313
132
133 .align 3
134 answer3:
135
136 .double 42.0
137 .double 44.0
138 .double 1.0
139
140 .align 3
141 answer4:
142
143 .float 42.0
144 .float 44.0
145 .float 1.0
146 .float 1000.0
147 .float -1152.0
148 .word 0xa5a5a5a5
149
150 .align 3
151 testdata4:
152
153 .float 42.0
154 .float 44.0
155 .float 1.0
156 .float 1000.0
157 .float -1152.0
158 .float -82.0
159 .word 0xa5a5a5a5
160
161 .align 3
162 answer5:
163
164 .short 0x5140 # 42 fp16
165 .short 0x5180 # 44 fp16
166 .short 0x3c00 # 1.0 fp16
167 .short 0x63d0 # 1000.0 fp16
168 .short 0xe480 # -1152.0 fp16
169 .short 0xd520 # -82 fp16
170 .short 0xa5a5
171 .short 0xa5a5
172 .dword 0xa5a5a5a5a5a5a5a5
173
174 .align 3
175 testdata6:
176
177 .float 42.0
178 .float 44.0
179 .float 1.0
180 .float 1000.0
181 .float -1152.0
182 .float -82.0
183 .dword 0x0
184 .dword 0x0
185 .dword 0x0
186 .dword 0x0
187 .dword 0x0
188 .dword 0x0
189 .dword 0x0
190
191 # Output data section.
192 RVTEST_DATA_BEGIN # Start of test output data region.
193 .align 3
194 result:
195 .dword -1
196 .dword -1
197 .dword -1
198 RVTEST_DATA_END # End of test output data region.
199