sort out registers and add extra unit tests for add-variable-elwidth
[riscv-tests.git] / isa / rv64ui / sv_add_elwidth.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6 #define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2 ) \
7 \
8 SV_LDD_DATA( x4, testdata , 0); \
9 SV_LDD_DATA( x5, testdata+8 , 0); \
10 SV_LDD_DATA( x12, testdata+16, 0); \
11 SV_LDD_DATA( x13, testdata+24, 0); \
12 \
13 li x14, 0; \
14 li x15, 0; \
15 \
16 SET_SV_MVL( 2); \
17 SET_SV_3CSRS( SV_REG_CSR( 1, 4, wid1, 4, 1), \
18 SV_REG_CSR( 1, 12, wid2, 12, 1), \
19 SV_REG_CSR( 1, 14, wid3, 14, 1)); \
20 SET_SV_VL( 2); \
21 \
22 add x14, x4, x12; \
23 \
24 CLR_SV_CSRS(); \
25 SET_SV_VL( 1); \
26 SET_SV_MVL( 1); \
27 \
28 TEST_SV_IMM( x14, expect1 ); \
29 TEST_SV_IMM( x15, expect2 ); \
30 TEST_SV_IMM( x12, 0x0000005242322212); \
31 TEST_SV_IMM( x13, 0x0000005141312111);
32
33
34 # SV test: vector-vector add
35 #
36 # sets up x3 and x4 with data, sets VL to 2, and carries out
37 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
38
39 # Test code region.
40 RVTEST_CODE_BEGIN # Start of test code.
41
42 #
43 SV_ELWIDTH_TEST( 0, 0, 0, 0x000000ab8b6b4b2b, 0x000000a888684828 )
44 SV_ELWIDTH_TEST( 0, 0, 3, 0x886848288b6b4b2b, 0x0000000000000000 )
45 SV_ELWIDTH_TEST( 1, 1, 0, 0x000000000000002b, 0x000000000000004b )
46
47 RVTEST_PASS # Signal success.
48 fail:
49 RVTEST_FAIL
50 RVTEST_CODE_END # End of test code.
51
52 # Input data section.
53 # This section is optional, and this data is NOT saved in the output.
54 .data
55 .align 3
56 testdata:
57 .dword 0x0000005949392919
58 .dword 0x0000005747372717
59 .dword 0x0000005242322212
60 .dword 0x0000005141312111
61
62 # Output data section.
63 RVTEST_DATA_BEGIN # Start of test output data region.
64 .align 3
65 result:
66 .dword -1
67 .dword -1
68 .dword -1
69 RVTEST_DATA_END # End of test output data region.
70