501be374319ec946fb6963e184efc26fa2c79abd
[riscv-tests.git] / isa / rv64ui / sv_add_elwidth.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6 #define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2 ) \
7 \
8 SV_LDD_DATA( x2, testdata , 0); \
9 SV_LDD_DATA( x3, testdata+8 , 0); \
10 SV_LDD_DATA( x4, testdata+16, 0); \
11 SV_LDD_DATA( x5, testdata+24, 0); \
12 \
13 li x28, 0; \
14 li x29, 0; \
15 \
16 SET_SV_MVL( 2); \
17 SET_SV_3CSRS( SV_REG_CSR( 1, 2, wid1, 2, 1), \
18 SV_REG_CSR( 1, 4, wid2, 4, 1), \
19 SV_REG_CSR( 1, 28, wid3, 28, 1)); \
20 SET_SV_VL( 2); \
21 \
22 add x28, x2, x4; \
23 \
24 CLR_SV_CSRS(); \
25 SET_SV_VL( 1); \
26 SET_SV_MVL( 1); \
27 \
28 TEST_SV_IMM( x28, expect1); \
29 TEST_SV_IMM( x29, expect2); \
30 TEST_SV_IMM( x4, 0x0000005242322212); \
31 TEST_SV_IMM( x5, 0x0000005141312111);
32
33
34 # SV test: vector-vector add
35 #
36 # sets up x3 and x4 with data, sets VL to 2, and carries out
37 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
38
39 # Test code region.
40 RVTEST_CODE_BEGIN # Start of test code.
41
42 #
43 SV_ELWIDTH_TEST( 0, 0, 0, 0x000000ab8b6b4b2b, 0x000000aa8a6a4a2a )
44 //SV_ELWIDTH_TEST( 0x2, 0, 0, 41, 43 )
45 //SV_ELWIDTH_TEST( 0x3, 0, 0, 42, 43 )
46 //SV_ELWIDTH_TEST( 0x0, 0, 0, 41, 42 )
47
48 RVTEST_PASS # Signal success.
49 fail:
50 RVTEST_FAIL
51 RVTEST_CODE_END # End of test code.
52
53 # Input data section.
54 # This section is optional, and this data is NOT saved in the output.
55 .data
56 .align 3
57 testdata:
58 .dword 0x0000005949392919
59 .dword 0x0000005747372717
60 .dword 0x0000005242322212
61 .dword 0x0000005141312111
62
63 # Output data section.
64 RVTEST_DATA_BEGIN # Start of test output data region.
65 .align 3
66 result:
67 .dword -1
68 .dword -1
69 .dword -1
70 RVTEST_DATA_END # End of test output data region.
71