e86a3f36c6a91f64ba1a38a3121c4d25e77a89fd
[riscv-tests.git] / isa / rv64ui / sv_addi.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6
7 # SV test: sets up x3 and x4 with data, sets VL to 2, and carries out
8 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
9
10 # Test code region.
11 RVTEST_CODE_BEGIN # Start of test code.
12
13 SV_LD_DATA( x2, testdata , 0)
14 SV_LD_DATA( x3, testdata+8 , 0)
15 SV_LD_DATA( x4, testdata+16, 0)
16 SV_LD_DATA( x5, testdata+24, 0)
17
18 SET_SV_MVL(2)
19 SET_SV_CSR(1, 3, 0, 3, 1, 0)
20 SET_SV_VL(2)
21
22 addi x3, x3, 1
23
24 CLR_SV_CSRS()
25 SET_SV_VL(0)
26 SET_SV_MVL(0)
27
28 TEST_SV_IMM(x2, 1001) # should not be modified
29 TEST_SV_IMM(x3, 42)
30 TEST_SV_IMM(x4, 43)
31 TEST_SV_IMM(x5, 1002) # should not be modified
32
33 RVTEST_PASS # Signal success.
34 fail:
35 RVTEST_FAIL
36 RVTEST_CODE_END # End of test code.
37
38 # Input data section.
39 # This section is optional, and this data is NOT saved in the output.
40 .data
41 .align 3
42 testdata:
43 .dword 1001
44 .dword 41
45 .dword 42
46 .dword 1002
47
48 # Output data section.
49 RVTEST_DATA_BEGIN # Start of test output data region.
50 .align 3
51 result:
52 .dword -1
53 .dword -1
54 .dword -1
55 RVTEST_DATA_END # End of test output data region.
56