isa/rv64ui/sv_addi_predicated_subvl.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6 #define SV_PREDICATION_TEST( pred, inv, zero, expect1, expect2 ) \
   7                                                         \
   8         SV_LDD_DATA( x2, testdata   , 0);               \
   9         SV_LDD_DATA( x3, testdata+8 , 0);               \
  10         SV_LDD_DATA( x4, testdata+16, 0);               \
  11         SV_LDD_DATA( x5, testdata+24, 0);               \
  12                                                         \
  13         li      x6, pred;                               \
  14                                                         \
  15         SET_SV_MVL( 2);                                  \
  16         SET_SV_CSR( 1, 3, SV_W_32BIT, 3, 1);             \
  17         SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0);         \
  18         SET_SV_VL( 2);                                   \
  19         SET_SV_SUBVL( 2);                                \
  20                                                         \
  21         addi    x3, x3, 1;                              \
  22                                                         \
  23         CLR_SV_CSRS();                                  \
  24         SET_SV_VL( 1);                                   \
  25         SET_SV_MVL( 1);                                  \
  26         SET_SV_SUBVL( 1);                                \
  27                                                         \
  28         TEST_SV_IMM( x2, 1001);                         \
  29         TEST_SV_IMM( x3, expect1);                       \
  30         TEST_SV_IMM( x4, expect2);                       \
  31         TEST_SV_IMM( x5, 1002);
  32
  33
  34 # SV test: vector-vector add
  35 #
  36 # sets up x3 and x4 with data, sets VL to 2, and carries out
  37 # an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
  38
  39 # Test code region.
  40 RVTEST_CODE_BEGIN   # Start of test code.
  41
  42         # no zeroing, no inversion
  43 /*
  44         SV_PREDICATION_TEST( 0x1, 0, 0, 0x4200000043, 0x4300000044 )
  45
  46         SV_PREDICATION_TEST( 0x2, 0, 0, 41, 43 )
  47 */
  48         //SV_PREDICATION_TEST( 0x3, 0, 0, 0x4200000043, 0x4400000045 )
  49         SV_PREDICATION_TEST( 0x0, 0, 0, 0x4100000042, 0x4300000044 )
  50 /*
  51         # zeroing, no inversion
  52         SV_PREDICATION_TEST( 0x1, 0, 1, 42, 0 )
  53         SV_PREDICATION_TEST( 0x2, 0, 1, 0, 43 )
  54         SV_PREDICATION_TEST( 0x3, 0, 1, 42, 43 )
  55         SV_PREDICATION_TEST( 0x0, 0, 1, 0, 0 )
  56
  57         # no zeroing, inversion
  58         SV_PREDICATION_TEST( 0x2, 1, 0, 42, 42 )
  59         SV_PREDICATION_TEST( 0x1, 1, 0, 41, 43 )
  60         SV_PREDICATION_TEST( 0x0, 1, 0, 42, 43 )
  61         SV_PREDICATION_TEST( 0x3, 1, 0, 41, 42 )
  62
  63         # zeroing, inversion
  64         SV_PREDICATION_TEST( 0x2, 1, 1, 42, 0 )
  65         SV_PREDICATION_TEST( 0x1, 1, 1, 0, 43 )
  66         SV_PREDICATION_TEST( 0x0, 1, 1, 42, 43 )
  67         SV_PREDICATION_TEST( 0x3, 1, 1, 0, 0 )
  68 */
  69
  70         RVTEST_PASS           # Signal success.
  71 fail:
  72         RVTEST_FAIL
  73 RVTEST_CODE_END     # End of test code.
  74
  75 # Input data section.
  76 # This section is optional, and this data is NOT saved in the output.
  77 .data
  78         .align 3
  79 testdata:
  80         .dword 1001
  81         .dword 0x4100000042
  82         .dword 0x4300000044
  83         .dword 1002
  84
  85 # Output data section.
  86 RVTEST_DATA_BEGIN   # Start of test output data region.
  87         .align 3
  88 result:
  89         .dword -1
  90         .dword -1
  91         .dword -1
  92 RVTEST_DATA_END     # End of test output data region.
  93