isa/rv64ui/sv_addi_vector_vector.S

   1 #include "riscv_test.h"
   2 #include "sv_test_macros.h"
   3
   4 RVTEST_RV64U        # Define TVM used by program.
   5
   6
   7 # SV test: vector-vector add different rd and rs1
   8 #
   9 # sets up x6 and x7 with data, sets VL to 2, and carries out
  10 # an "x3 = 1 + x6".  which actually means "x3 = 1 + x6 *AND* x4 = 1 + x7"
  11
  12 # Test code region.
  13 RVTEST_CODE_BEGIN   # Start of test code.
  14
  15         SV_LD_DATA( x2, testdata   , 0)
  16         SV_LD_DATA( x6, testdata+8 , 0)
  17         SV_LD_DATA( x7, testdata+16, 0)
  18         SV_LD_DATA( x5, testdata+24, 0)
  19
  20         li          x3, 0 # deliberately set x3 to 0 (target of add)
  21         li          x4, 0 # deliberately set x4 to 0
  22
  23         SET_SV_MVL(2)
  24         SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
  25                       SV_REG_CSR(1, 6, 0, 6, 1, 0) )
  26         SET_SV_VL(2)
  27
  28         addi    x3, x6, 1
  29
  30         CLR_SV_CSRS()
  31         SET_SV_VL(0)
  32         SET_SV_MVL(0)
  33
  34         TEST_SV_IMM(x2, 1001) # should not be modified
  35         TEST_SV_IMM(x3, 42)
  36         TEST_SV_IMM(x4, 43)
  37         TEST_SV_IMM(x5, 1002) # should not be modified
  38
  39         RVTEST_PASS           # Signal success.
  40 fail:
  41         RVTEST_FAIL
  42 RVTEST_CODE_END     # End of test code.
  43
  44 # Input data section.
  45 # This section is optional, and this data is NOT saved in the output.
  46 .data
  47         .align 3
  48 testdata:
  49         .dword 1001
  50         .dword 41
  51         .dword 42
  52         .dword 1002
  53
  54 # Output data section.
  55 RVTEST_DATA_BEGIN   # Start of test output data region.
  56         .align 3
  57 result:
  58         .dword -1
  59         .dword -1
  60         .dword -1
  61 RVTEST_DATA_END     # End of test output data region.
  62