1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
4 RVTEST_RV64U # Define TVM used by program.
6 #define SV_ELWIDTH_TEST( inst, vl, wid1, wid2, \
7 testdata, expect1, expect2, expect3 ) \
11 li x28, 0xa5a5a5a5a5a5a5a5; \
12 li x29, 0xa5a5a5a5a5a5a5a5; \
13 li x30, 0xa5a5a5a5a5a5a5a5; \
16 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, 0), \
17 SV_REG_CSR( 1, 28, wid2, 28, 1)); \
26 TEST_SV_IMM( x28, expect1 ); \
27 TEST_SV_IMM( x29, expect2 ); \
28 TEST_SV_IMM( x30, expect3 );
31 # SV test: vector-vector add
33 # sets up x3 and x4 with data, sets VL to 2, and carries out
34 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
37 RVTEST_CODE_BEGIN # Start of test code.
39 SV_ELWIDTH_TEST( ld , 2, SV_W_DFLT, SV_W_DFLT, testdata1,
40 0x8979695949392919, 0x8777675747372717, 0xa5a5a5a5a5a5a5a5 )
41 SV_ELWIDTH_TEST( ld , 3, SV_W_DFLT, SV_W_DFLT, testdata1,
42 0x8979695949392919, 0x8777675747372717, 0x8676665646362616 )
43 SV_ELWIDTH_TEST( ld , 3, SV_W_16BIT, SV_W_DFLT, testdata1,
44 0x0000000000002919, 0x0000000000004939, 0x0000000000006959 )
45 SV_ELWIDTH_TEST( ld , 5, SV_W_16BIT, SV_W_32BIT, testdata1,
46 0x0000493900002919, 0xffff897900006959, 0xa5a5a5a500002717 )
47 SV_ELWIDTH_TEST( ld , 5, SV_W_32BIT, SV_W_16BIT, testdata1,
48 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 )
49 SV_ELWIDTH_TEST( ld , 7, SV_W_16BIT, SV_W_8BIT, testdata1,
50 0xa557371779593919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 )
51 SV_ELWIDTH_TEST( ld , 11, SV_W_8BIT, SV_W_16BIT, testdata1,
52 0x0049003900290019, 0xff89007900690059, 0xa5a5003700270017 )
53 RVTEST_PASS # Signal success.
56 RVTEST_CODE_END # End of test code.
59 # This section is optional, and this data is NOT saved in the output.
63 .dword 0x8979695949392919
64 .dword 0x8777675747372717
65 .dword 0x8676665646362616
66 .dword 0x8272625242322212
67 .dword 0x8171615141312111
68 .dword 0x8373635343332313
70 # Output data section.
71 RVTEST_DATA_BEGIN # Start of test output data region.
77 RVTEST_DATA_END # End of test output data region.