add isvec args to test elwidth macros
[riscv-tests.git] / isa / rv64ui / sv_st_elwidth.S
1 #include "riscv_test.h"
2 #include "sv_test_macros.h"
3
4 RVTEST_RV64U # Define TVM used by program.
5
6 #define SV_ELWIDTH_TEST( sinst, vl, elwidth, wid1, wid2, isvec1, isvec2, \
7 testdata, expect1, expect2, expect3 ) \
8 \
9 la x12, testtarget ; \
10 la x13, (testtarget+elwidth); \
11 la x14, (testtarget+elwidth*2); \
12 la x15, (testtarget+elwidth*3); \
13 la x16, (testtarget+elwidth*4); \
14 la x17, (testtarget+elwidth*5); \
15 \
16 li t0, 0xa5a5a5a5a5a5a5a5; \
17 la t1, testtarget; \
18 sd t0, 0(t1); \
19 sd t0, elwidth(t1); \
20 sd t0, elwidth*2(t1); \
21 \
22 ld x28, testdata; \
23 ld x29, (testdata+elwidth); \
24 ld x30, (testdata+elwidth*2); \
25 \
26 SET_SV_MVL( vl); \
27 SET_SV_2CSRS( SV_REG_CSR( 1, 12, wid1, 12, isvec1), \
28 SV_REG_CSR( 1, 28, wid2, 28, isvec2)); \
29 SET_SV_VL( vl ); \
30 \
31 sinst x28, 0(x12); \
32 \
33 CLR_SV_CSRS(); \
34 SET_SV_VL( 1); \
35 SET_SV_MVL( 1); \
36 \
37 ld x28, testtarget; \
38 ld x29, (testtarget+elwidth); \
39 ld x30, (testtarget+elwidth*2); \
40 \
41 TEST_SV_IMM( x28, expect1 ); \
42 TEST_SV_IMM( x29, expect2 ); \
43 TEST_SV_IMM( x30, expect3 );
44
45
46 # SV test: vector-vector add
47 #
48 # sets up x3 and x4 with data, sets VL to 2, and carries out
49 # an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4"
50
51 # Test code region.
52 RVTEST_CODE_BEGIN # Start of test code.
53
54 SV_ELWIDTH_TEST( sd , 2, 8, SV_W_DFLT, SV_W_DFLT, 1, 1, testdata1,
55 0x8979695949392919, 0x8777675747372717, 0xa5a5a5a5a5a5a5a5 )
56 SV_ELWIDTH_TEST( sd , 3, 8, SV_W_DFLT, SV_W_DFLT, 1, 1, testdata1,
57 0x8979695949392919, 0x8777675747372717, 0x8676665646362616 )
58 SV_ELWIDTH_TEST( sd , 3, 8, SV_W_16BIT, SV_W_DFLT, 1, 1, testdata1,
59 0xa5a5261627172919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 )
60 SV_ELWIDTH_TEST( sd , 5, 8, SV_W_16BIT, SV_W_32BIT, 1, 1, testdata1,
61 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 )
62 SV_ELWIDTH_TEST( sd , 5, 8, SV_W_32BIT, SV_W_16BIT, 1, 1, testdata1,
63 0x0000493900002919, 0x0000897900006959, 0xa5a5a5a500002717 )
64 SV_ELWIDTH_TEST( sd , 7, 8, SV_W_16BIT, SV_W_8BIT, 1, 1, testdata1,
65 0x0049003900290019, 0xa5a5007900690059, 0xa5a5a5a5a5a5a5a5 )
66 SV_ELWIDTH_TEST( sd , 11, 8, SV_W_8BIT, SV_W_16BIT, 1, 1, testdata1,
67 0x7757371779593919, 0xa5a5a5a5a5563616, 0xa5a5a5a5a5a5a5a5 )
68 RVTEST_PASS # Signal success.
69 fail:
70 RVTEST_FAIL
71 RVTEST_CODE_END # End of test code.
72
73 # Input data section.
74 # This section is optional, and this data is NOT saved in the output.
75 .data
76 .align 3
77 testdata1:
78 .dword 0x8979695949392919
79 .dword 0x8777675747372717
80 .dword 0x8676665646362616
81 .dword 0x8272625242322212
82 .dword 0x8171615141312111
83 .dword 0x8373635343332313
84 testtarget:
85 .dword 0x0
86 .dword 0x0
87 .dword 0x0
88 .dword 0x0
89 .dword 0x0
90 .dword 0x0
91
92 # Output data section.
93 RVTEST_DATA_BEGIN # Start of test output data region.
94 .align 3
95 result:
96 .dword -1
97 .dword -1
98 .dword -1
99 RVTEST_DATA_END # End of test output data region.
100