Use `gdb_report_register_access_error enable`

[riscv-tests.git] / debug / targets / RISC-V / spike-rtos.cfg

diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 159a70fac42c7ffcaa6af1f1371ef43f0f73fdce..d8bd27e903aa333b4bf7b5d2cf970fd367404b64 100644 (file)
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -12,6 +12,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
+gdb_report_register_access_error enable
 
 # Expose an unimplemented CSR so we can test non-existent register access
 # behavior.