add twin-predicated sv c_mv unit test (no zeroing)

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 23feaa1c287a3372aa7ad1ba049b3289dda37797..421d0c3b66fe984555dfdcc8cbaea11ff4652817 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -16,6 +16,10 @@
         li     x1, c1 | ((c2)<<16); \
         csrrw  x0, 0x4c0, x1
 
+#define SET_SV_2PREDCSRS( c1, c2 ) \
+        li     x1, c1 | ((c2)<<16); \
+        csrrw  x0, 0x4c8, x1
+
 #define CLR_SV_CSRS( ) csrrw   x0, 0x4c0, 0
 #define CLR_SV_PRED_CSRS( ) csrrw   x0, 0x4c8, 0