alter unit tests to match change in CSR table format

[riscv-tests.git] / isa / macros / simplev / sv_test_macros.h

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index ddf951aab96c6ed422683ff7b1602868437e8cde..b3b06c03127fa0d0bf709b4797141890dd2bfdab 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -1,15 +1,14 @@
-#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
+#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
+  (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
+  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
 
-#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
-  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
-
-#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
-        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
+        li     x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
         csrrw  x0, 0x4c0, x1
 
-#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
-        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
+        li     x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
         csrrw  x0, 0x4c8, x1
 
 #define SET_SV_2CSRS( c1, c2 ) \