Verify that mtval/stval is written correctly on misaligned fetch

[riscv-tests.git] / isa / rv64si / ma_fetch.S

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index a97eecb6cbf394d2604250a87fbc737dca40e666..eb50f944fdbb187138ae94d23c298732b469e880 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -17,6 +17,7 @@ RVTEST_CODE_BEGIN
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause
+  #define sbadaddr mbadaddr
   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler
@@ -32,9 +33,10 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 2
 1:
   .option rvc
-  c.j fail
+  c.j 1f
   c.j 2f
   .option norvc
+1:
   j fail
 2:
 
@@ -53,9 +55,53 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 3
 1:
   .option rvc
-  c.j fail
+  c.j 1f
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with jal instead of jalr.
+  li TESTNUM, 5
+  li t1, 0
+  la t0, 1f
+  jal t1, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
   c.j 2f
   .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with a taken branch instead of jalr.
+  li TESTNUM, 6
+  li t1, 0
+  la t0, 1f
+  beqz x0, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Not-taken branches should not trap, even without RVC.
+  li TESTNUM, 7
+  bnez x0, 1f
+  j 2f
+  .option rvc
+  c.j 1f
+1:
+  c.j 1f
+  .option norvc
+1:
   j fail
 2:
 
@@ -63,12 +109,17 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
-  # tests 2 and 4 should trap
+  # tests 2, 4, 5, and 6 should trap
   li a0, 2
   beq TESTNUM, a0, 1f
   li a0, 4
   beq TESTNUM, a0, 1f
+  li a0, 5
+  beq TESTNUM, a0, 1f
+  li a0, 6
+  beq TESTNUM, a0, 1f
   j fail
 1:
 
@@ -82,9 +133,16 @@ stvec_handler:
 
   # verify that epc == &jalr (== t0 - 4)
   csrr a1, sepc
-  addi t0, t0, -4
+  addi a1, a1, 4
   bne t0, a1, fail
 
+  # verify that badaddr == 0 or badaddr == t0+2.
+  csrr a0, sbadaddr
+  beqz a0, 1f
+  addi a0, a0, -2
+  bne a0, t0, fail
+1:
+
   addi a1, a1, 12
   csrw sepc, a1
   sret