Verify that mtval/stval is written correctly on misaligned fetch

[riscv-tests.git] / isa / rv64si / ma_fetch.S

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index ae8377de98d0a51b7c4460e180960841e2bc118f..eb50f944fdbb187138ae94d23c298732b469e880 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -13,17 +13,32 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sbadaddr mbadaddr
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+#endif
+
+  .option norvc
 
-#ifndef __rvc
+  # Without RVC, the jalr should trap, and the handler will skip ahead.
+  # With RVC, the jalr should not trap, and "j fail" should get skipped.
   li TESTNUM, 2
   li t1, 0
   la t0, 1f
   jalr t1, t0, 2
+1:
+  .option rvc
+  c.j 1f
+  c.j 2f
+  .option norvc
 1:
   j fail
-#endif
+2:
 
   // This test should pass, since JALR ignores the target LSB
   li TESTNUM, 3
@@ -34,25 +49,77 @@ RVTEST_CODE_BEGIN
   j fail
 1:
 
-#ifndef __rvc
   li TESTNUM, 4
   li t1, 0
-  la t0, 3f
-  jr t0, 3
-3:
+  la t0, 1f
+  jalr t1, t0, 3
+1:
+  .option rvc
+  c.j 1f
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Like test 2, but with jal instead of jalr.
+  li TESTNUM, 5
+  li t1, 0
+  la t0, 1f
+  jal t1, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
   j fail
-#endif
+2:
+
+  # Like test 2, but with a taken branch instead of jalr.
+  li TESTNUM, 6
+  li t1, 0
+  la t0, 1f
+  beqz x0, 2f
+1:
+  .option rvc
+  c.j 1f
+2:
+  c.j 2f
+  .option norvc
+1:
+  j fail
+2:
+
+  # Not-taken branches should not trap, even without RVC.
+  li TESTNUM, 7
+  bnez x0, 1f
+  j 2f
+  .option rvc
+  c.j 1f
+1:
+  c.j 1f
+  .option norvc
+1:
+  j fail
+2:
 
   j pass
 
   TEST_PASSFAIL
 
-stvec:
-  # tests 2 and 4 should trap
+  .align 2
+stvec_handler:
+  # tests 2, 4, 5, and 6 should trap
   li a0, 2
   beq TESTNUM, a0, 1f
   li a0, 4
   beq TESTNUM, a0, 1f
+  li a0, 5
+  beq TESTNUM, a0, 1f
+  li a0, 6
+  beq TESTNUM, a0, 1f
   j fail
 1:
 
@@ -66,10 +133,17 @@ stvec:
 
   # verify that epc == &jalr (== t0 - 4)
   csrr a1, sepc
-  addi t0, t0, -4
+  addi a1, a1, 4
   bne t0, a1, fail
 
-  addi a1, a1, 8
+  # verify that badaddr == 0 or badaddr == t0+2.
+  csrr a0, sbadaddr
+  beqz a0, 1f
+  addi a0, a0, -2
+  bne a0, t0, fail
+1:
+
+  addi a1, a1, 12
   csrw sepc, a1
   sret