modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / Makefrag.sv

diff --git a/isa/rv64uc/Makefrag.sv b/isa/rv64uc/Makefrag.sv
index 52571ae6d61d2dba03c85e4127016ff087d436db..b97e6a078c0fffcccc6ac6a28a22be53bae28180 100644 (file)
--- a/isa/rv64uc/Makefrag.sv
+++ b/isa/rv64uc/Makefrag.sv
@@ -8,6 +8,7 @@ rv64uc_sv_tests = \
        sv_c_lwsp \
        sv_c_lwsp_predication \
        sv_c_swsp \
+       sv_c_beqz \
 
 rv64uc_p_tests = $(addprefix rv64uc-p-, $(rv64uc_sv_tests))
 rv64uc_v_tests = $(addprefix rv64uc-v-, $(rv64uc_sv_tests))