modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_lwsp.S

diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S
index e30d11abac647043d088657ce161e22b7b152be9..38dcaa2135ce134ce287e7d9c7374a248b389444 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp.S
+++ b/isa/rv64uc/sv_c_lwsp.S
@@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a1