modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_lwsp_predication.S

diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S
index a0a293434e492d9ae34277a71cd6b3855418fec1..0885dd7923cb9ac78a1df444637ab1b038fd87e8 100644 (file)
--- a/isa/rv64uc/sv_c_lwsp_predication.S
+++ b/isa/rv64uc/sv_c_lwsp_predication.S
@@ -45,9 +45,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a6