modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_mv.S

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index 11a042b920aa4fb18efb2b7763bb55d61924b981..ce8dd412a3e56572a7bca2b1f974f173f40da7a4 100644 (file)
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -31,9 +31,9 @@ RVTEST_CODE_BEGIN   # Start of test code.
         c.mv    x3, x6
         .option norvc
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x3, 1001) # should not be modified
         TEST_SV_IMM(x4, 41)