modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_mv_predication.S

diff --git a/isa/rv64uc/sv_c_mv_predication.S b/isa/rv64uc/sv_c_mv_predication.S
index fc0bb7498ba41933cc260819773cd5560442e0aa..7345de0facb6800acd8eed103c0245e249392e99 100644 (file)
--- a/isa/rv64uc/sv_c_mv_predication.S
+++ b/isa/rv64uc/sv_c_mv_predication.S
@@ -28,9 +28,9 @@ RVTEST_RV64U        # Define TVM used by program.
         c.mv    x3, x6;                                \
         .option norvc;                                 \
                                                        \
-        SET_SV_VL(0);                                  \
+        SET_SV_VL(1);                                  \
         CLR_SV_CSRS();                                 \
-        SET_SV_MVL(0);                                 \
+        SET_SV_MVL(1);                                 \
                                                        \
         TEST_SV_IMM(x3, expect1);                      \
         TEST_SV_IMM(x4, expect2);                      \