modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64uc / sv_c_swsp.S

diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index 7990707e7c1ce2ac5a6f7936c3a4d69fa217ac2a..622ca9eb37f95e2d0d9d3326e06fe12b9491490a 100644 (file)
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -37,9 +37,9 @@ RVTEST_CODE_BEGIN
   .option pop
 
 
-        SET_SV_VL(0)
+        SET_SV_VL(1)
         CLR_SV_CSRS()
-        SET_SV_MVL(0)
+        SET_SV_MVL(1)
 
   mv sp, a1