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modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)
[riscv-tests.git]
/
isa
/
rv64ud
/
sv_fadd.S
diff --git
a/isa/rv64ud/sv_fadd.S
b/isa/rv64ud/sv_fadd.S
index 9057dff8e1c2ef531fd871bffb9ef07512a9ee64..5818a2b8a59efe1c19faa446693b666e79d4bcb8 100644
(file)
--- a/
isa/rv64ud/sv_fadd.S
+++ b/
isa/rv64ud/sv_fadd.S
@@
-29,8
+29,8
@@
RVTEST_CODE_BEGIN # Start of test code.
fadd.d f2, f2, f6;
CLR_SV_CSRS()
- SET_SV_VL(
0
)
- SET_SV_MVL(
0
)
+ SET_SV_VL(
1
)
+ SET_SV_MVL(
1
)
TEST_SV_FD(0, f1, testdata+64, 0)
TEST_SV_FD(0, f2, testdata+72, 0)