alter unit tests to match change in CSR table format

[riscv-tests.git] / isa / rv64ui / sv_addi_predicated.S

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
index 32902f0e4f6aa1fad925f0f3052a31c66e56cc11..46246ea849eb0ebb92077526fc549dc4eaae4af5 100644 (file)
--- a/isa/rv64ui/sv_addi_predicated.S
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -13,8 +13,8 @@ RVTEST_RV64U        # Define TVM used by program.
         li      x6, pred;                               \
                                                         \
         SET_SV_MVL( 2);                                  \
-        SET_SV_CSR( 1, 3, 0, 3, 1, 0);                   \
-        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1);         \
+        SET_SV_CSR( 1, 3, 0, 3, 1);                    \
+        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0);         \
         SET_SV_VL( 2);                                   \
                                                         \
         addi    x3, x3, 1;                              \