modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ui / sv_addi_predicated.S

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
index 46246ea849eb0ebb92077526fc549dc4eaae4af5..8bea7f8f75b12b4bacbd4b0cf8e1bdbbb60ec7b4 100644 (file)
--- a/isa/rv64ui/sv_addi_predicated.S
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -20,8 +20,8 @@ RVTEST_RV64U        # Define TVM used by program.
         addi    x3, x3, 1;                              \
                                                         \
         CLR_SV_CSRS();                                  \
-        SET_SV_VL( 0);                                   \
-        SET_SV_MVL( 0);                                  \
+        SET_SV_VL( 1);                                   \
+        SET_SV_MVL( 1);                                  \
                                                         \
         TEST_SV_IMM( x2, 1001);                         \
         TEST_SV_IMM( x3, expect1);                       \