modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ui / sv_addi_scalar_src.S

diff --git a/isa/rv64ui/sv_addi_scalar_src.S b/isa/rv64ui/sv_addi_scalar_src.S
index e17df23dc92cfca61a2ff0a43b91c97a34e91955..edb0345febc8546daa14660aa5735e66c4437d1c 100644 (file)
--- a/isa/rv64ui/sv_addi_scalar_src.S
+++ b/isa/rv64ui/sv_addi_scalar_src.S
@@ -27,8 +27,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x3, x6, 1 # x3 = x6+1 *AND* x4 = x6+1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)