modified VL and MVL CSRs to range from 1-XLEN rather than 0-(XLEN-1)

[riscv-tests.git] / isa / rv64ui / sv_addi_vector_vector.S

diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S
index 8594ba7566f38efe007411888f50862eee5c6d60..b616e13ddd044db56bd4d5dec3f65d157664a79d 100644 (file)
--- a/isa/rv64ui/sv_addi_vector_vector.S
+++ b/isa/rv64ui/sv_addi_vector_vector.S
@@ -28,8 +28,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         addi    x3, x6, 1
 
         CLR_SV_CSRS()
-        SET_SV_VL(0)
-        SET_SV_MVL(0)
+        SET_SV_VL(1)
+        SET_SV_MVL(1)
 
         TEST_SV_IMM(x2, 1001) # should not be modified
         TEST_SV_IMM(x3, 42)