Remove instruction width assumptions to support RVC

diff --git a/env b/env
index 92fb0bd7d7d2723f90896bb351f5cdb0eb36b73b..ae484b6ab8aec310ecb0ca9a46704a709d0ef99d 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 92fb0bd7d7d2723f90896bb351f5cdb0eb36b73b
+Subproject commit ae484b6ab8aec310ecb0ca9a46704a709d0ef99d

diff --git a/isa/rv32ui/fence_i.S b/isa/rv32ui/fence_i.S
index 8785c1eb8fa6ca46210009ebffc06045874e6908..cd1dbc3cb97f2d52738eb54d8d4e1acd162c0bc0 100644 (file)
--- a/isa/rv32ui/fence_i.S
+++ b/isa/rv32ui/fence_i.S
@@ -1,53 +1,7 @@
 # See LICENSE for license details.
 
-#*****************************************************************************
-# fence_i.S
-#-----------------------------------------------------------------------------
-#
-# Test self-modifying code and the fence.i instruction.
-#
-
 #include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-li a3, 111
-la a0, 3f
-la a1, 1f
-la a2, 2f
-lw a0, 0(a0)
-
-# test I$ hit
-.align 6
-sw a0, 0(a1)
-fence.i
-
-1: addi a3, a3, 222
-TEST_CASE( 2, a3, 444, nop )
-
-# test prefetcher hit
-li a4, 100
-1: addi a4, a4, -1
-bnez a4, 1b
-
-sw a0, 0(a2)
-fence.i
-
-.align 6
-2: addi a3, a3, 555
-TEST_CASE( 3, a3, 777, nop )
-
-3: addi a3, a3, 333
-
-TEST_PASSFAIL
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
+#undef RVTEST_RV64U
+#define RVTEST_RV64U RVTEST_RV32U
 
-RVTEST_DATA_END
+#include "../rv64ui/fence_i.S"

diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 66ed5a085317dfe082bb71b523e165e91fd452a7..0314cf5acbfc64914e89b388e90fc856f088ae0b 100644 (file)
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -52,6 +52,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   csrr t0, scause
   li t1, 2

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
index ed177f5a11682ff5c70acb958e427c12b7bd2c59..c84242a99c4d9d817305f50bde104375e59d154e 100644 (file)
--- a/isa/rv64mi/ma_addr.S
+++ b/isa/rv64mi/ma_addr.S
@@ -14,6 +14,7 @@ RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
   .align 3
+  .option norvc
   auipc s0, 0
 
   # indicate it's a load test

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 35fc99a52feed5f0cc7a5613983ab4075afbb65d..3858daad556f3632d5d5c2f8035f3a5c62dbf79b 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -61,6 +61,7 @@ RVTEST_CODE_BEGIN
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   # Trapping on tests 10 and 11 is good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index a97eecb6cbf394d2604250a87fbc737dca40e666..544daa0140a2703b6754ad7b14cc73b22f1d734c 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -63,6 +63,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   # tests 2 and 4 should trap
   li a0, 2

diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index 99240be53474006d6fe8c8772ca5bc13ae9aa5eb..c2a6e49ef70a76db72f99db3b66f1dac89c5d134 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -23,21 +23,18 @@ RVTEST_CODE_BEGIN
 #endif
 
   li TESTNUM, 2
+
   sbreak
   j fail
 
-  j pass
-
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
   bne t0, t1, fail
-  csrr t0, sepc
-  addi t0, t0, 8
-  csrw sepc, t0
-  sret
+  j pass
 
 RVTEST_CODE_END
 

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index f4752d15e9dd05027e407bd612baa3d403eed58b..82ba7c0cbc81619d46a9cf8ff4f555509047cfc4 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -39,6 +39,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   li t1, CAUSE_USER_ECALL
   csrr t0, scause

diff --git a/isa/rv64ui/fence_i.S b/isa/rv64ui/fence_i.S
index 2c51c9cc9f2763c3821a9087f1f97e192c319075..f2076c8f54c2d71d6058c7502b0176f0c05607ec 100644 (file)
--- a/isa/rv64ui/fence_i.S
+++ b/isa/rv64ui/fence_i.S
@@ -22,6 +22,7 @@ lw a0, 0(a0)
 # test I$ hit
 .align 6
 sw a0, 0(a1)
+.align 2
 fence.i
 
 1: addi a3, a3, 222

diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index 210973ede7b2dd6a6e3f0c95e57819c006ce683e..d63bbe206a7f41d72fdde61e67bdb541e2cfd579 100644 (file)
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -42,6 +42,8 @@ target_2:
   # Test delay slot instructions not executed nor bypassed
   #-------------------------------------------------------------
 
+  .option push
+  .option norvc
   TEST_CASE( 7, t0, 4, \
     li  t0, 1; \
     la  t1, 1f; \
@@ -53,6 +55,7 @@ target_2:
 1:  addi t0, t0, 1; \
     addi t0, t0, 1; \
   )
+  .option pop
 
   TEST_PASSFAIL