src_dir := .
include $(src_dir)/rv64ui/Makefrag
+include $(src_dir)/rv64um/Makefrag
+include $(src_dir)/rv64ua/Makefrag
include $(src_dir)/rv64uf/Makefrag
include $(src_dir)/rv64ud/Makefrag
include $(src_dir)/rv64si/Makefrag
include $(src_dir)/rv64mi/Makefrag
include $(src_dir)/rv32ui/Makefrag
+include $(src_dir)/rv32um/Makefrag
+include $(src_dir)/rv32ua/Makefrag
include $(src_dir)/rv32si/Makefrag
include $(src_dir)/rv32mi/Makefrag
endef
$(eval $(call compile_template,rv32ui,-m32))
+$(eval $(call compile_template,rv32um,-m32))
+$(eval $(call compile_template,rv32ua,-m32))
$(eval $(call compile_template,rv32si,-m32))
$(eval $(call compile_template,rv32mi,-m32))
ifeq ($(XLEN),64)
$(eval $(call compile_template,rv64ui))
+$(eval $(call compile_template,rv64um))
+$(eval $(call compile_template,rv64ua))
$(eval $(call compile_template,rv64uf))
$(eval $(call compile_template,rv64ud))
$(eval $(call compile_template,rv64si))
--- /dev/null
+#=======================================================================
+# Makefrag for rv32ua tests
+#-----------------------------------------------------------------------
+
+rv32ua_sc_tests = \
+ amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+ lrsc \
+
+rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
+rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
+
+spike_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x7ffff800, \
+ li a1, 0x80000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x80000000, \
+ li a1, 0x80000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 1; \
+ sw x0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffff; \
+ sw x0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffff; \
+ sw x0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffff; \
+ sw x0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffff800, \
+ li a1, 1; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffff800, \
+ li a1, 0x80000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0x80000000, \
+ li a0, 0x80000000; \
+ li a1, 0xfffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x7ffff800, \
+ li a1, 0xc0000001; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+# get a unique core id
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+ la a0, foo; \
+ sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
+TEST_CASE( 3, a4, 1, \
+ la a0, foo; \
+ add a1, a0, 1024; \
+ lr.w a1, (a1); \
+ sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
+la a0, foo
+li a1, 1000
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 1000*ncores*(ncores-1)/2
+TEST_CASE( 4, a2, 0, \
+ la a0, foo; \
+ li a1, 500; \
+ mul a1, a1, a3; \
+ add a2, a3, -1; \
+ mul a1, a1, a2; \
+ lw a2, (a0); \
+ sub a2, a2, a1; \
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+RVTEST_DATA_END
rv32ui_sc_tests = \
simple \
add addi \
- amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
- lrsc \
and andi \
auipc \
beq bge bgeu blt bltu bne \
- div divu \
fence_i \
j jal jalr \
lb lbu lh lhu lw \
lui \
- mul mulh mulhu mulhsu \
or ori \
- rem remu \
sb sh sw \
sll slli \
slt slti \
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoadd_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x7ffff800, \
- li a1, 0x80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoand.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x80000000, \
- li a1, 0x80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 1; \
- sw x0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 1, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffff; \
- sw x0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoor.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffff800, \
- li a1, 1; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoswap_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoswap.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoswap.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffff800, \
- li a1, 0x80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoswap.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoxor_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoxor.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0x80000000, \
- li a0, 0x80000000; \
- li a1, 0xfffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoxor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x7ffff800, \
- li a1, 0xc0000001; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoxor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# div.S
-#-----------------------------------------------------------------------------
-#
-# Test div instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, div, 3, 20, 6 );
- TEST_RR_OP( 3, div, -3, -20, 6 );
- TEST_RR_OP( 4, div, -3, 20, -6 );
- TEST_RR_OP( 5, div, 3, -20, -6 );
-
- TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
- TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
-
- TEST_RR_OP( 8, div, -1, -1<<63, 0 );
- TEST_RR_OP( 9, div, -1, 1, 0 );
- TEST_RR_OP(10, div, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divu.S
-#-----------------------------------------------------------------------------
-#
-# Test divu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divu, 3, 20, 6 );
- TEST_RR_OP( 3, divu, 715827879, -20, 6 );
- TEST_RR_OP( 4, divu, 0, 20, -6 );
- TEST_RR_OP( 5, divu, 0, -20, -6 );
-
- TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
- TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
-
- TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
- TEST_RR_OP( 9, divu, -1, 1, 0 );
- TEST_RR_OP(10, divu, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divuw.S
-#-----------------------------------------------------------------------------
-#
-# Test divuw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divuw, 3, 20, 6 );
- TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 );
- TEST_RR_OP( 4, divuw, 0, 20, -6 );
- TEST_RR_OP( 5, divuw, 0, -20, -6 );
-
- TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 );
- TEST_RR_OP( 7, divuw, 0, -1<<31, -1 );
-
- TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
- TEST_RR_OP( 9, divuw, -1, 1, 0 );
- TEST_RR_OP(10, divuw, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divw.S
-#-----------------------------------------------------------------------------
-#
-# Test divw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divw, 3, 20, 6 );
- TEST_RR_OP( 3, divw, -3, -20, 6 );
- TEST_RR_OP( 4, divw, -3, 20, -6 );
- TEST_RR_OP( 5, divw, 3, -20, -6 );
-
- TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 );
- TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
-
- TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
- TEST_RR_OP( 9, divw, -1, 1, 0 );
- TEST_RR_OP(10, divw, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# lrsr.S
-#-----------------------------------------------------------------------------
-#
-# Test LR/SC instructions.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
-# get a unique core id
-la a0, coreid
-li a1, 1
-amoadd.w a2, a1, (a0)
-
-# for now, only run this on core 0
-1:li a3, 1
-bgeu a2, a3, 1b
-
-1: lw a1, (a0)
-bltu a1, a3, 1b
-
-# make sure that sc without a reservation fails.
-TEST_CASE( 2, a4, 1, \
- la a0, foo; \
- sc.w a4, x0, (a0); \
-)
-
-# make sure that sc with the wrong reservation fails.
-# TODO is this actually mandatory behavior?
-TEST_CASE( 3, a4, 1, \
- la a0, foo; \
- add a1, a0, 1024; \
- lr.w a1, (a1); \
- sc.w a4, a1, (a0); \
-)
-
-# have each core add its coreid to foo 1000 times
-la a0, foo
-li a1, 1000
-1: lr.w a4, (a0)
-add a4, a4, a2
-sc.w a4, a4, (a0)
-bnez a4, 1b
-add a1, a1, -1
-bnez a1, 1b
-
-# wait for all cores to finish
-la a0, barrier
-li a1, 1
-amoadd.w x0, a1, (a0)
-1: lw a1, (a0)
-blt a1, a3, 1b
-fence
-
-# expected result is 1000*ncores*(ncores-1)/2
-TEST_CASE( 4, a2, 0, \
- la a0, foo; \
- li a1, 500; \
- mul a1, a1, a3; \
- add a2, a3, -1; \
- mul a1, a1, a2; \
- lw a2, (a0); \
- sub a2, a2, a1; \
-)
-
-TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-coreid: .word 0
-barrier: .word 0
-foo: .word 0
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mul.S
-#-----------------------------------------------------------------------------
-#
-# Test mul instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
- TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
-
- TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
- TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
- TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
-
- TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
- TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
-
- TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
-
- TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
- TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
- TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
- TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
- TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
-
- TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
- TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
- TEST_RR_ZEROSRC12( 28, mul, 0 );
- TEST_RR_ZERODEST( 29, mul, 33, 34 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulh.S
-#-----------------------------------------------------------------------------
-#
-# Test mulh instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
- TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
- TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
-
- TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
- TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
-
- TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
-
- TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
- TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
- TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
-
- TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
- TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
- TEST_RR_ZEROSRC12( 28, mulh, 0 );
- TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulhsu.S
-#-----------------------------------------------------------------------------
-#
-# Test mulhsu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
- TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
- TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
-
- TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
- TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
-
- TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
-
- TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
- TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
- TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
- TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
- TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
- TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
-
-
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulhu.S
-#-----------------------------------------------------------------------------
-#
-# Test mulhu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
- TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
- TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
-
- TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
- TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
-
- TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
-
- TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
- TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
- TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
-
- TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
- TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
- TEST_RR_ZEROSRC12( 28, mulhu, 0 );
- TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
-
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulw.S
-#-----------------------------------------------------------------------------
-#
-# Test mulw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulw, 0x00000000, 0x00000000, 0xffff8000 );
- TEST_RR_OP( 6, mulw, 0x00000000, 0x80000000, 0x00000000 );
- TEST_RR_OP( 7, mulw, 0x00000000, 0x80000000, 0xffff8000 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
- TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
- TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
-
- TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
- TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
- TEST_RR_ZEROSRC12( 28, mulw, 0 );
- TEST_RR_ZERODEST( 29, mulw, 33, 34 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# rem.S
-#-----------------------------------------------------------------------------
-#
-# Test rem instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, rem, 2, 20, 6 );
- TEST_RR_OP( 3, rem, -2, -20, 6 );
- TEST_RR_OP( 4, rem, 2, 20, -6 );
- TEST_RR_OP( 5, rem, -2, -20, -6 );
-
- TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
- TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
-
- TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
- TEST_RR_OP( 9, rem, 1, 1, 0 );
- TEST_RR_OP(10, rem, 0, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# remu.S
-#-----------------------------------------------------------------------------
-#
-# Test remu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV32U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, remu, 2, 20, 6 );
- TEST_RR_OP( 3, remu, 2, -20, 6 );
- TEST_RR_OP( 4, remu, 20, 20, -6 );
- TEST_RR_OP( 5, remu, -20, -20, -6 );
-
- TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
- TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
-
- TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
- TEST_RR_OP( 9, remu, 1, 1, 0 );
- TEST_RR_OP(10, remu, 0, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
--- /dev/null
+#=======================================================================
+# Makefrag for rv32um tests
+#-----------------------------------------------------------------------
+
+rv32um_sc_tests = \
+ div divu \
+ mul mulh mulhsu mulhu \
+ rem remu \
+
+rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
+rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
+
+spike_tests += $(rv32um_p_tests) $(rv32um_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, div, 3, 20, 6 );
+ TEST_RR_OP( 3, div, -3, -20, 6 );
+ TEST_RR_OP( 4, div, -3, 20, -6 );
+ TEST_RR_OP( 5, div, 3, -20, -6 );
+
+ TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
+ TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+ TEST_RR_OP( 9, div, -1, 1, 0 );
+ TEST_RR_OP(10, div, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divu, 3, 20, 6 );
+ TEST_RR_OP( 3, divu, 715827879, -20, 6 );
+ TEST_RR_OP( 4, divu, 0, 20, -6 );
+ TEST_RR_OP( 5, divu, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divu, -1, 1, 0 );
+ TEST_RR_OP(10, divu, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 );
+ TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 );
+
+ TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mul, 0 );
+ TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 );
+
+ TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulh, 0 );
+ TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+ TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 );
+
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 );
+ TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 );
+
+ TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d );
+ TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab );
+
+ TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 );
+
+ TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff );
+ TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 );
+ TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 );
+
+ TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 );
+ TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 );
+ TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+ TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 );
+
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, rem, 2, 20, 6 );
+ TEST_RR_OP( 3, rem, -2, -20, 6 );
+ TEST_RR_OP( 4, rem, 2, 20, -6 );
+ TEST_RR_OP( 5, rem, -2, -20, -6 );
+
+ TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
+
+ TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, rem, 1, 1, 0 );
+ TEST_RR_OP(10, rem, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remu, 2, 20, 6 );
+ TEST_RR_OP( 3, remu, 2, -20, 6 );
+ TEST_RR_OP( 4, remu, 20, 20, -6 );
+ TEST_RR_OP( 5, remu, -20, -20, -6 );
+
+ TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, remu, 1, 1, 0 );
+ TEST_RR_OP(10, remu, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+#=======================================================================
+# Makefrag for rv64ua tests
+#-----------------------------------------------------------------------
+
+rv64ua_sc_tests = \
+ amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
+ amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
+ lrsc \
+
+rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests))
+rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests))
+
+spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoadd.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff7ffff800, \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoadd.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoadd_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoadd.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x000000007ffff800, \
+ li a1, 0xffffffff80000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoadd.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoand.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff80000000, \
+ li a1, 0x0000000080000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoand.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoand.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoand.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xffffffff80000000, \
+ li a1, 0x0000000080000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoand.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomax.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 1; \
+ sd x0, 0(a3); \
+ amomax.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 1, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomax_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomax.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 1; \
+ sw x0, 0(a3); \
+ amomax.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 1, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomaxu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amomaxu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomaxu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomaxu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amomaxu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amomin.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amomin.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amomin_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amomin.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amomin.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ amominu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sd x0, 0(a3); \
+ amominu.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amominu_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amominu.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_CASE(4, a4, 0, \
+ li a1, 0xffffffffffffffff; \
+ sw x0, 0(a3); \
+ amominu.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 1; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoor.w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 1; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap.d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoswap.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 0x0000000080000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoswap.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoswap_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoswap.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sw a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0xfffffffffffff800, \
+ li a1, 0x0000000080000000; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ add a5, a5, a4; \
+ lw x0, 0(a5); \
+ amoswap.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_d.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoxor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x000000007ffff800, \
+ li a1, 1; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoxor.d a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ TEST_CASE(2, a4, 0xffffffff80000000, \
+ li a0, 0xffffffff80000000; \
+ li a1, 0xfffffffffffff800; \
+ la a3, amo_operand; \
+ sd a0, 0(a3); \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ nop; nop; nop; nop; \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
+
+ # try again after a cache miss
+ TEST_CASE(4, a4, 0x000000007ffff800, \
+ li a1, 0xc0000001; \
+ li a4, 16384; \
+ add a5, a3, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ add a5, a5, a4; \
+ ld x0, 0(a5); \
+ amoxor.w a4, a1, 0(a3); \
+ )
+
+ TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3))
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
+
+ .bss
+ .align 3
+amo_operand:
+ .dword 0
+ .skip 65536
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# lrsr.S
+#-----------------------------------------------------------------------------
+#
+# Test LR/SC instructions.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+# get a unique core id
+la a0, coreid
+li a1, 1
+amoadd.w a2, a1, (a0)
+
+# for now, only run this on core 0
+1:li a3, 1
+bgeu a2, a3, 1b
+
+1: lw a1, (a0)
+bltu a1, a3, 1b
+
+# make sure that sc without a reservation fails.
+TEST_CASE( 2, a4, 1, \
+ la a0, foo; \
+ sc.w a4, x0, (a0); \
+)
+
+# make sure that sc with the wrong reservation fails.
+# TODO is this actually mandatory behavior?
+TEST_CASE( 3, a4, 1, \
+ la a0, foo; \
+ add a1, a0, 1024; \
+ lr.w a1, (a1); \
+ sc.w a4, a1, (a0); \
+)
+
+# have each core add its coreid to foo 1000 times
+la a0, foo
+li a1, 1000
+1: lr.w a4, (a0)
+add a4, a4, a2
+sc.w a4, a4, (a0)
+bnez a4, 1b
+add a1, a1, -1
+bnez a1, 1b
+
+# wait for all cores to finish
+la a0, barrier
+li a1, 1
+amoadd.w x0, a1, (a0)
+1: lw a1, (a0)
+blt a1, a3, 1b
+fence
+
+# expected result is 1000*ncores*(ncores-1)/2
+TEST_CASE( 4, a2, 0, \
+ la a0, foo; \
+ li a1, 500; \
+ mul a1, a1, a3; \
+ add a2, a3, -1; \
+ mul a1, a1, a2; \
+ lw a2, (a0); \
+ sub a2, a2, a1; \
+)
+
+TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+coreid: .word 0
+barrier: .word 0
+foo: .word 0
+RVTEST_DATA_END
rv64ui_sc_tests = \
add addi addiw addw \
- amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \
- amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
- lrsc \
and andi \
auipc \
beq bge bgeu blt bltu bne \
- div divu divuw divw \
example simple \
fence_i \
j jal jalr \
lb lbu lh lhu lw lwu ld \
lui \
- mul mulh mulhsu mulhu mulw \
or ori \
- rem remu remuw remw \
sb sh sw sd \
sll slli slliw sllw \
slt slti sltiu sltu \
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoadd_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoadd.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xffffffff7ffff800, \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoadd.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoadd_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoadd.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x000000007ffff800, \
- li a1, 0xffffffff80000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoadd.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoand_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoand.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xffffffff80000000, \
- li a1, 0x0000000080000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoand.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoand.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoand.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xffffffff80000000, \
- li a1, 0x0000000080000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoand.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomax.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 1; \
- sd x0, 0(a3); \
- amomax.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 1, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomax_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomax.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 1; \
- sw x0, 0(a3); \
- amomax.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 1, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomaxu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amomaxu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomaxu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomaxu.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sw x0, 0(a3); \
- amomaxu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amomin.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amomin.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amomin_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amomin.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sw x0, 0(a3); \
- amomin.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- amominu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sd x0, 0(a3); \
- amominu.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amominu_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amominu.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3))
-
- TEST_CASE(4, a4, 0, \
- li a1, 0xffffffffffffffff; \
- sw x0, 0(a3); \
- amominu.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoor_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 1; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoor.w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoor.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 1; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoswap.d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoswap.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoswap.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 0x0000000080000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoswap.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoswap_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoswap.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sw a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoswap.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0xfffffffffffff800, \
- li a1, 0x0000000080000000; \
- li a4, 16384; \
- add a5, a3, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- add a5, a5, a4; \
- lw x0, 0(a5); \
- amoswap.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoxor_d.S
-#-----------------------------------------------------------------------------
-#
-# Test amoxor.d instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoxor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x000000007ffff800, \
- li a1, 1; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoxor.d a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# amoxor_w.S
-#-----------------------------------------------------------------------------
-#
-# Test amoxor.w instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- TEST_CASE(2, a4, 0xffffffff80000000, \
- li a0, 0xffffffff80000000; \
- li a1, 0xfffffffffffff800; \
- la a3, amo_operand; \
- sd a0, 0(a3); \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- nop; nop; nop; nop; \
- amoxor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3))
-
- # try again after a cache miss
- TEST_CASE(4, a4, 0x000000007ffff800, \
- li a1, 0xc0000001; \
- li a4, 16384; \
- add a5, a3, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- add a5, a5, a4; \
- ld x0, 0(a5); \
- amoxor.w a4, a1, 0(a3); \
- )
-
- TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3))
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
-
- .bss
- .align 3
-amo_operand:
- .dword 0
- .skip 65536
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# div.S
-#-----------------------------------------------------------------------------
-#
-# Test div instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, div, 3, 20, 6 );
- TEST_RR_OP( 3, div, -3, -20, 6 );
- TEST_RR_OP( 4, div, -3, 20, -6 );
- TEST_RR_OP( 5, div, 3, -20, -6 );
-
- TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
- TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
-
- TEST_RR_OP( 8, div, -1, -1<<63, 0 );
- TEST_RR_OP( 9, div, -1, 1, 0 );
- TEST_RR_OP(10, div, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divu.S
-#-----------------------------------------------------------------------------
-#
-# Test divu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divu, 3, 20, 6 );
- TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 );
- TEST_RR_OP( 4, divu, 0, 20, -6 );
- TEST_RR_OP( 5, divu, 0, -20, -6 );
-
- TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 );
- TEST_RR_OP( 7, divu, 0, -1<<63, -1 );
-
- TEST_RR_OP( 8, divu, -1, -1<<63, 0 );
- TEST_RR_OP( 9, divu, -1, 1, 0 );
- TEST_RR_OP(10, divu, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divuw.S
-#-----------------------------------------------------------------------------
-#
-# Test divuw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divuw, 3, 20, 6 );
- TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 );
- TEST_RR_OP( 4, divuw, 0, 20, -6 );
- TEST_RR_OP( 5, divuw, 0, -20, -6 );
-
- TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 );
- TEST_RR_OP( 7, divuw, 0, -1<<31, -1 );
-
- TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
- TEST_RR_OP( 9, divuw, -1, 1, 0 );
- TEST_RR_OP(10, divuw, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# divw.S
-#-----------------------------------------------------------------------------
-#
-# Test divw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, divw, 3, 20, 6 );
- TEST_RR_OP( 3, divw, -3, -20, 6 );
- TEST_RR_OP( 4, divw, -3, 20, -6 );
- TEST_RR_OP( 5, divw, 3, -20, -6 );
-
- TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 );
- TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
-
- TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
- TEST_RR_OP( 9, divw, -1, 1, 0 );
- TEST_RR_OP(10, divw, -1, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# lrsr.S
-#-----------------------------------------------------------------------------
-#
-# Test LR/SC instructions.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
-# get a unique core id
-la a0, coreid
-li a1, 1
-amoadd.w a2, a1, (a0)
-
-# for now, only run this on core 0
-1:li a3, 1
-bgeu a2, a3, 1b
-
-1: lw a1, (a0)
-bltu a1, a3, 1b
-
-# make sure that sc without a reservation fails.
-TEST_CASE( 2, a4, 1, \
- la a0, foo; \
- sc.w a4, x0, (a0); \
-)
-
-# make sure that sc with the wrong reservation fails.
-# TODO is this actually mandatory behavior?
-TEST_CASE( 3, a4, 1, \
- la a0, foo; \
- add a1, a0, 1024; \
- lr.w a1, (a1); \
- sc.w a4, a1, (a0); \
-)
-
-# have each core add its coreid to foo 1000 times
-la a0, foo
-li a1, 1000
-1: lr.w a4, (a0)
-add a4, a4, a2
-sc.w a4, a4, (a0)
-bnez a4, 1b
-add a1, a1, -1
-bnez a1, 1b
-
-# wait for all cores to finish
-la a0, barrier
-li a1, 1
-amoadd.w x0, a1, (a0)
-1: lw a1, (a0)
-blt a1, a3, 1b
-fence
-
-# expected result is 1000*ncores*(ncores-1)/2
-TEST_CASE( 4, a2, 0, \
- la a0, foo; \
- li a1, 500; \
- mul a1, a1, a3; \
- add a2, a3, -1; \
- mul a1, a1, a2; \
- lw a2, (a0); \
- sub a2, a2, a1; \
-)
-
-TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-coreid: .word 0
-barrier: .word 0
-foo: .word 0
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mul.S
-#-----------------------------------------------------------------------------
-#
-# Test mul instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 );
- TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
-
- TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
- TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
- TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
- TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
-
- TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
- TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
- TEST_RR_ZEROSRC12( 28, mul, 0 );
- TEST_RR_ZERODEST( 29, mul, 33, 34 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulh.S
-#-----------------------------------------------------------------------------
-#
-# Test mulh instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 );
-
- TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 );
- TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 );
- TEST_RR_ZEROSRC12( 28, mulh, 0 );
- TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulhsu.S
-#-----------------------------------------------------------------------------
-#
-# Test mulhsu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
-
- TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 );
- TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 );
- TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
- TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulhu.S
-#-----------------------------------------------------------------------------
-#
-# Test mulhu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
- TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 );
-
- TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 );
- TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 );
- TEST_RR_ZEROSRC12( 28, mulhu, 0 );
- TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# mulw.S
-#-----------------------------------------------------------------------------
-#
-# Test mulw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 );
- TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 );
- TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 );
-
- TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
- TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
- TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
-
- #-------------------------------------------------------------
- # Source/Destination tests
- #-------------------------------------------------------------
-
- TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
- TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
- TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
-
- #-------------------------------------------------------------
- # Bypassing tests
- #-------------------------------------------------------------
-
- TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
- TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
- TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
-
- TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
- TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
-
- TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
- TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
- TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
- TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
-
- TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
- TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
- TEST_RR_ZEROSRC12( 28, mulw, 0 );
- TEST_RR_ZERODEST( 29, mulw, 33, 34 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# rem.S
-#-----------------------------------------------------------------------------
-#
-# Test rem instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, rem, 2, 20, 6 );
- TEST_RR_OP( 3, rem, -2, -20, 6 );
- TEST_RR_OP( 4, rem, 2, 20, -6 );
- TEST_RR_OP( 5, rem, -2, -20, -6 );
-
- TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
- TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
-
- TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
- TEST_RR_OP( 9, rem, 1, 1, 0 );
- TEST_RR_OP(10, rem, 0, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# remu.S
-#-----------------------------------------------------------------------------
-#
-# Test remu instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, remu, 2, 20, 6 );
- TEST_RR_OP( 3, remu, 2, -20, 6 );
- TEST_RR_OP( 4, remu, 20, 20, -6 );
- TEST_RR_OP( 5, remu, -20, -20, -6 );
-
- TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
- TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
-
- TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
- TEST_RR_OP( 9, remu, 1, 1, 0 );
- TEST_RR_OP(10, remu, 0, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# remuw.S
-#-----------------------------------------------------------------------------
-#
-# Test remuw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, remuw, 2, 20, 6 );
- TEST_RR_OP( 3, remuw, 2, -20, 6 );
- TEST_RR_OP( 4, remuw, 20, 20, -6 );
- TEST_RR_OP( 5, remuw, -20, -20, -6 );
-
- TEST_RR_OP( 6, remuw, 0, -1<<31, 1 );
- TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 );
-
- TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 );
- TEST_RR_OP( 9, remuw, 1, 1, 0 );
- TEST_RR_OP(10, remuw, 0, 0, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
+++ /dev/null
-# See LICENSE for license details.
-
-#*****************************************************************************
-# remw.S
-#-----------------------------------------------------------------------------
-#
-# Test remw instruction.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64U
-RVTEST_CODE_BEGIN
-
- #-------------------------------------------------------------
- # Arithmetic tests
- #-------------------------------------------------------------
-
- TEST_RR_OP( 2, remw, 2, 20, 6 );
- TEST_RR_OP( 3, remw, -2, -20, 6 );
- TEST_RR_OP( 4, remw, 2, 20, -6 );
- TEST_RR_OP( 5, remw, -2, -20, -6 );
-
- TEST_RR_OP( 6, remw, 0, -1<<31, 1 );
- TEST_RR_OP( 7, remw, 0, -1<<31, -1 );
-
- TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 );
- TEST_RR_OP( 9, remw, 1, 1, 0 );
- TEST_RR_OP(10, remw, 0, 0, 0 );
- TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 );
-
- TEST_PASSFAIL
-
-RVTEST_CODE_END
-
- .data
-RVTEST_DATA_BEGIN
-
- TEST_DATA
-
-RVTEST_DATA_END
--- /dev/null
+#=======================================================================
+# Makefrag for rv64um tests
+#-----------------------------------------------------------------------
+
+rv64um_sc_tests = \
+ div divu divuw divw \
+ mul mulh mulhsu mulhu mulw \
+ rem remu remuw remw \
+
+rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests))
+rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests))
+
+spike_tests += $(rv64um_p_tests) $(rv64um_v_tests)
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# div.S
+#-----------------------------------------------------------------------------
+#
+# Test div instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, div, 3, 20, 6 );
+ TEST_RR_OP( 3, div, -3, -20, 6 );
+ TEST_RR_OP( 4, div, -3, 20, -6 );
+ TEST_RR_OP( 5, div, 3, -20, -6 );
+
+ TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
+ TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, div, -1, -1<<63, 0 );
+ TEST_RR_OP( 9, div, -1, 1, 0 );
+ TEST_RR_OP(10, div, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divu.S
+#-----------------------------------------------------------------------------
+#
+# Test divu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divu, 3, 20, 6 );
+ TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 );
+ TEST_RR_OP( 4, divu, 0, 20, -6 );
+ TEST_RR_OP( 5, divu, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 );
+ TEST_RR_OP( 7, divu, 0, -1<<63, -1 );
+
+ TEST_RR_OP( 8, divu, -1, -1<<63, 0 );
+ TEST_RR_OP( 9, divu, -1, 1, 0 );
+ TEST_RR_OP(10, divu, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divuw.S
+#-----------------------------------------------------------------------------
+#
+# Test divuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divuw, 3, 20, 6 );
+ TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 );
+ TEST_RR_OP( 4, divuw, 0, 20, -6 );
+ TEST_RR_OP( 5, divuw, 0, -20, -6 );
+
+ TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divuw, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divuw, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divuw, -1, 1, 0 );
+ TEST_RR_OP(10, divuw, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# divw.S
+#-----------------------------------------------------------------------------
+#
+# Test divw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, divw, 3, 20, 6 );
+ TEST_RR_OP( 3, divw, -3, -20, 6 );
+ TEST_RR_OP( 4, divw, -3, 20, -6 );
+ TEST_RR_OP( 5, divw, 3, -20, -6 );
+
+ TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 );
+ TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 );
+
+ TEST_RR_OP( 8, divw, -1, -1<<31, 0 );
+ TEST_RR_OP( 9, divw, -1, 1, 0 );
+ TEST_RR_OP(10, divw, -1, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mul.S
+#-----------------------------------------------------------------------------
+#
+# Test mul instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 );
+ TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 );
+
+ TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+ TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mul, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mul, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mul, 0 );
+ TEST_RR_ZERODEST( 29, mul, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulh.S
+#-----------------------------------------------------------------------------
+#
+# Test mulh instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 );
+
+ TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 );
+ TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 );
+ TEST_RR_ZEROSRC12( 28, mulh, 0 );
+ TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhsu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhsu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 );
+ TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 );
+ TEST_RR_ZEROSRC12( 28, mulhsu, 0 );
+ TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulhu.S
+#-----------------------------------------------------------------------------
+#
+# Test mulhu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d );
+ TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 );
+
+ TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 );
+ TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 );
+ TEST_RR_ZEROSRC12( 28, mulhu, 0 );
+ TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mulw.S
+#-----------------------------------------------------------------------------
+#
+# Test mulw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 );
+ TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 );
+ TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 );
+
+ TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 );
+ TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 );
+ TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 );
+
+ #-------------------------------------------------------------
+ # Source/Destination tests
+ #-------------------------------------------------------------
+
+ TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 );
+ TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 );
+
+ #-------------------------------------------------------------
+ # Bypassing tests
+ #-------------------------------------------------------------
+
+ TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 );
+ TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 );
+ TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 );
+
+ TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 );
+ TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 );
+
+ TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 );
+ TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 );
+ TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 );
+ TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 );
+
+ TEST_RR_ZEROSRC1( 26, mulw, 0, 31 );
+ TEST_RR_ZEROSRC2( 27, mulw, 0, 32 );
+ TEST_RR_ZEROSRC12( 28, mulw, 0 );
+ TEST_RR_ZERODEST( 29, mulw, 33, 34 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# rem.S
+#-----------------------------------------------------------------------------
+#
+# Test rem instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, rem, 2, 20, 6 );
+ TEST_RR_OP( 3, rem, -2, -20, 6 );
+ TEST_RR_OP( 4, rem, 2, 20, -6 );
+ TEST_RR_OP( 5, rem, -2, -20, -6 );
+
+ TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
+
+ TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, rem, 1, 1, 0 );
+ TEST_RR_OP(10, rem, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remu.S
+#-----------------------------------------------------------------------------
+#
+# Test remu instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remu, 2, 20, 6 );
+ TEST_RR_OP( 3, remu, 2, -20, 6 );
+ TEST_RR_OP( 4, remu, 20, 20, -6 );
+ TEST_RR_OP( 5, remu, -20, -20, -6 );
+
+ TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
+ TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
+
+ TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
+ TEST_RR_OP( 9, remu, 1, 1, 0 );
+ TEST_RR_OP(10, remu, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remuw.S
+#-----------------------------------------------------------------------------
+#
+# Test remuw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remuw, 2, 20, 6 );
+ TEST_RR_OP( 3, remuw, 2, -20, 6 );
+ TEST_RR_OP( 4, remuw, 20, 20, -6 );
+ TEST_RR_OP( 5, remuw, -20, -20, -6 );
+
+ TEST_RR_OP( 6, remuw, 0, -1<<31, 1 );
+ TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 );
+
+ TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 );
+ TEST_RR_OP( 9, remuw, 1, 1, 0 );
+ TEST_RR_OP(10, remuw, 0, 0, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
--- /dev/null
+# See LICENSE for license details.
+
+#*****************************************************************************
+# remw.S
+#-----------------------------------------------------------------------------
+#
+# Test remw instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64U
+RVTEST_CODE_BEGIN
+
+ #-------------------------------------------------------------
+ # Arithmetic tests
+ #-------------------------------------------------------------
+
+ TEST_RR_OP( 2, remw, 2, 20, 6 );
+ TEST_RR_OP( 3, remw, -2, -20, 6 );
+ TEST_RR_OP( 4, remw, 2, 20, -6 );
+ TEST_RR_OP( 5, remw, -2, -20, -6 );
+
+ TEST_RR_OP( 6, remw, 0, -1<<31, 1 );
+ TEST_RR_OP( 7, remw, 0, -1<<31, -1 );
+
+ TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 );
+ TEST_RR_OP( 9, remw, 1, 1, 0 );
+ TEST_RR_OP(10, remw, 0, 0, 0 );
+ TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 );
+
+ TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+ .data
+RVTEST_DATA_BEGIN
+
+ TEST_DATA
+
+RVTEST_DATA_END
projects / riscv-tests.git / commitdiff