Merge pull request #52 from riscv/vcs_sim_cmd

debug: Correct the calling for a 32-bit simulation target

diff --git a/isa/rv32mi/shamt.S b/isa/rv32mi/shamt.S
index 2c92412d6e6bc526f16b2dd655f186363e269b1f..aa136b5f7b0cd4fc88fc1ed468f102c1c5057ab5 100644 (file)
--- a/isa/rv32mi/shamt.S
+++ b/isa/rv32mi/shamt.S
@@ -17,7 +17,7 @@ RVTEST_CODE_BEGIN
   TEST_CASE( 2, a0, 65536, li a0, 1; slli a0, a0, 16);
 
   # Make sure slli with shamt[5] set is not legal.
-  TEST_CASE( 3, x0, 1, slli a0, a0, 32);
+  TEST_CASE( 3, x0, 1, .word 0x02051513); # slli a0, a0, 32
 
   TEST_PASSFAIL