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debug: working with newprogram branch
author
Megan Wachs
<megan@sifive.com>
Fri, 14 Apr 2017 14:56:32 +0000
(07:56 -0700)
committer
Megan Wachs
<megan@sifive.com>
Fri, 14 Apr 2017 14:56:32 +0000
(07:56 -0700)
debug/targets.py
patch
|
blob
|
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debug/targets/freedom-e300-sim/openocd.cfg
patch
|
blob
|
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debug/targets/freedom-u500-sim/openocd.cfg
patch
|
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debug/testlib.py
patch
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diff --git
a/debug/targets.py
b/debug/targets.py
index 52b623cc59262353b4a84d4582b1a862c1438588..043652cdbeca7732298da1ddb26045db232a61a8 100644
(file)
--- a/
debug/targets.py
+++ b/
debug/targets.py
@@
-99,7
+99,7
@@
class HiFive1Target(FreedomE300Target):
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
- timeout_sec =
24
0
+ timeout_sec =
600
0
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
@@
-119,7
+119,7
@@
class FreedomU500Target(Target):
class FreedomU500SimTarget(Target):
name = "freedom-u500-sim"
xlen = 64
class FreedomU500SimTarget(Target):
name = "freedom-u500-sim"
xlen = 64
- timeout_sec =
24
0
+ timeout_sec =
600
0
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
diff --git
a/debug/targets/freedom-e300-sim/openocd.cfg
b/debug/targets/freedom-e300-sim/openocd.cfg
index 0b808858a410a53f876d02fec4a5fc42c52e42e2..f3d9cb43a596f8fd90263d0cfaebff33da5c2903 100644
(file)
--- a/
debug/targets/freedom-e300-sim/openocd.cfg
+++ b/
debug/targets/freedom-e300-sim/openocd.cfg
@@
-7,8
+7,7
@@
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-rtos riscv
init
init
-
halt
halt
diff --git
a/debug/targets/freedom-u500-sim/openocd.cfg
b/debug/targets/freedom-u500-sim/openocd.cfg
index 0b808858a410a53f876d02fec4a5fc42c52e42e2..9239c83ddde91c20de939040bee122b3ab03292a 100644
(file)
--- a/
debug/targets/freedom-u500-sim/openocd.cfg
+++ b/
debug/targets/freedom-u500-sim/openocd.cfg
@@
-2,13
+2,15
@@
adapter_khz 10000
source [find interface/jtag_vpi.cfg]
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
source [find interface/jtag_vpi.cfg]
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port 44005
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-rtos riscv
init
halt
init
halt
+echo "OK GO NOW"
diff --git
a/debug/testlib.py
b/debug/testlib.py
index a762174df18240a2309d3f8def20f14ff998d3c5..5a5d6e360def979992c6b567215936b600d51e25 100644
(file)
--- a/
debug/testlib.py
+++ b/
debug/testlib.py
@@
-166,7
+166,7
@@
class Openocd(object):
messaged = False
while True:
log = open(Openocd.logname).read()
messaged = False
while True:
log = open(Openocd.logname).read()
- if "
Examined RISCV core
" in log:
+ if "
OK GO NOW
" in log:
break
if not self.process.poll() is None:
raise Exception(
break
if not self.process.poll() is None:
raise Exception(
@@
-203,7
+203,7
@@
class Openocd(object):
elif matches:
[match] = matches
return int(match.group('port'))
elif matches:
[match] = matches
return int(match.group('port'))
- time.sleep(
0.
1)
+ time.sleep(1)
raise Exception("Timed out waiting for gdb server to obtain port.")
def __del__(self):
raise Exception("Timed out waiting for gdb server to obtain port.")
def __del__(self):
@@
-261,7
+261,7
@@
class Gdb(object):
"""Wait for prompt."""
self.child.expect(r"\(gdb\)")
"""Wait for prompt."""
self.child.expect(r"\(gdb\)")
- def command(self, command, timeout=
-1
):
+ def command(self, command, timeout=
6000
):
self.child.sendline(command)
self.child.expect("\n", timeout=timeout)
self.child.expect(r"\(gdb\)", timeout=timeout)
self.child.sendline(command)
self.child.expect("\n", timeout=timeout)
self.child.expect(r"\(gdb\)", timeout=timeout)
@@
-278,7
+278,7
@@
class Gdb(object):
def interrupt(self):
self.child.send("\003")
def interrupt(self):
self.child.send("\003")
- self.child.expect(r"\(gdb\)", timeout=60)
+ self.child.expect(r"\(gdb\)", timeout=60
00
)
return self.child.before.strip()
def x(self, address, size='w'):
return self.child.before.strip()
def x(self, address, size='w'):
@@
-311,7
+311,7
@@
class Gdb(object):
return output
def load(self):
return output
def load(self):
- output = self.command("load", timeout=60)
+ output = self.command("load", timeout=60
00
)
assert "failed" not in output
assert "Transfer rate" in output
assert "failed" not in output
assert "Transfer rate" in output