la t0, trap_entry
csrw mtvec, t0
csrwi mstatus, 0
+
+ // make sure these registers exist by seeing if either S or U bits
+ // are set before attempting to zero them out.
+ csrr t1, misa
+ addi t2, x0, 1
+ slli t2, t2, 20 // U_EXTENSION
+ and t2, t1, t2
+ bne x0, t2, 1f
+ addi t2, x0, 1
+ slli t2, t2, 18 // S_EXTENSION
+ and t2, t1, t2
+ bne x0, t2, 1f
+ j 2f
+1:
csrwi mideleg, 0
csrwi medeleg, 0
+2:
csrwi mie, 0
# initialize global pointer
# update mstatus
csrr t1, CSR_MSTATUS
#if XLEN == 32
- li t0, (MSTATUS_MPRV | (VM_SV32 << 24))
+ li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV32 << 24))
#else
- li t0, (MSTATUS_MPRV | (VM_SV39 << 24))
+ li t0, (MSTATUS_MPRV | (SPTBR_MODE_SV39 << 24))
#endif
#li t0, ((VM_SV39 << 24))
or t1, t0, t1
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
- timeout_sec = 240
+ timeout_sec = 6000
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
class FreedomU500SimTarget(Target):
name = "freedom-u500-sim"
xlen = 64
- timeout_sec = 240
+ timeout_sec = 6000
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1 -rtos riscv
flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
source [find interface/jtag_vpi.cfg]
jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port 34448
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
init
-
halt
+echo "OK GO NOW"
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
gdb_report_data_abort enable
adapter_khz 10000
source [find interface/jtag_vpi.cfg]
-jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+jtag_vpi_set_port 46401
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
init
halt
+echo "OK GO NOW"
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
init
return None
def compile(args, xlen=32): # pylint: disable=redefined-builtin
- cc = os.path.expandvars("$RISCV/bin/riscv%d-unknown-elf-gcc" % xlen)
+ cc = os.path.expandvars("$RISCV/bin/riscv64-unknown-elf-gcc")
cmd = [cc, "-g"]
+ if (xlen == 32):
+ cmd.append("-march=rv32imac")
+ cmd.append("-mabi=ilp32")
+ else:
+ cmd.append("-march=rv64imac")
+ cmd.append("-mabi=lp64")
for arg in args:
found = find_file(arg)
if found:
else:
cmd.append(arg)
process = subprocess.Popen(cmd, stdout=subprocess.PIPE,
- stderr=subprocess.PIPE)
+ stderr=subprocess.PIPE)
stdout, stderr = process.communicate()
if process.returncode:
print
messaged = False
while True:
log = open(Openocd.logname).read()
- if "Examined RISCV core" in log:
+ if "OK GO NOW" in log:
break
if not self.process.poll() is None:
raise Exception(
elif matches:
[match] = matches
return int(match.group('port'))
- time.sleep(0.1)
+ time.sleep(1)
raise Exception("Timed out waiting for gdb server to obtain port.")
def __del__(self):
"""Wait for prompt."""
self.child.expect(r"\(gdb\)")
- def command(self, command, timeout=-1):
+ def command(self, command, timeout=6000):
self.child.sendline(command)
self.child.expect("\n", timeout=timeout)
self.child.expect(r"\(gdb\)", timeout=timeout)
def interrupt(self):
self.child.send("\003")
- self.child.expect(r"\(gdb\)", timeout=60)
+ self.child.expect(r"\(gdb\)", timeout=6000)
return self.child.before.strip()
def x(self, address, size='w'):
return output
def load(self):
- output = self.command("load", timeout=60)
+ output = self.command("load", timeout=6000)
assert "failed" not in output
assert "Transfer rate" in output
projects / riscv-tests.git / commitdiff