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Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 11:36:50 +0000 (11:36 +0000)]
add riscvdefs.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 10:31:26 +0000 (10:31 +0000)]
remove sync set output_state
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 07:55:23 +0000 (07:55 +0000)]
sort out memory_interface_fetch_address
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:56:49 +0000 (03:56 +0000)]
add some arbitrary math into example
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:52:20 +0000 (03:52 +0000)]
call value_bits_sign direct
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:45:44 +0000 (03:45 +0000)]
can`t stand list incomprehension
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:44:24 +0000 (03:44 +0000)]
add example pipeline.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:08:15 +0000 (00:08 +0000)]
corrections, clash fetch_action and self.fetch_action
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:01:27 +0000 (00:01 +0000)]
add conversion code, see what happens
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 22:35:59 +0000 (22:35 +0000)]
more cleanup
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 19:12:39 +0000 (19:12 +0000)]
cleanup, use sync instead of comb where appropriate
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 02:02:56 +0000 (02:02 +0000)]
add cpudefs.py
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 00:21:59 +0000 (00:21 +0000)]
reorg case statement
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 15:11:28 +0000 (15:11 +0000)]
convert case statement
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 14:38:42 +0000 (14:38 +0000)]
converting cpu_fetch_stage to migen
Jacob Lifshay [Wed, 21 Mar 2018 01:19:21 +0000 (18:19 -0700)]
add licenses and readme
projects / rv32.git / log