src/peripherals/flexbus/FlexBus_Types.bsv

   1 // Copyright (c) 2017 Bluespec, Inc.  All Rights Reserved
   2
   3 package FlexBus_Types;
   4
   5 // ================================================================
   6 // See export list below
   7 // ================================================================
   8 // Exports
   9
  10 export
  11
  12 // RTL-level interfaces (signals/buses)
  13 FlexBus_Slave_IFC (..),
  14 FlexBus_Master_IFC (..),
  15
  16
  17 // Higher-level enums and structs for the FlexBus
  18 FlexBus_States (..),
  19
  20 FlexBus_Payload (..),
  21 FlexBus_Attr (..),
  22 FlexBus_din (..),
  23 FlexBus_Signals (..),
  24
  25 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
  26 FlexBus_Register_IFC (..),
  27 FlexBus_Register_Output_IFC (..),
  28 FlexBus_Register_Input_IFC (..),
  29
  30 AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
  31
  32 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
  33 mkAXI4_Slave_to_FlexBus_Master_Xactor;
  34
  35 // ================================================================
  36 // BSV library imports
  37
  38 import Vector      :: *;
  39 import FIFOF       :: *;
  40 import GetPut   :: *;
  41 import SpecialFIFOs:: *;
  42 import Connectable :: *;
  43 import ConfigReg :: *;
  44 `include "defined_parameters.bsv"
  45
  46 // ----------------
  47 // BSV additional libs
  48
  49 import Semi_FIFOF :: *;
  50 import AXI4_Types   :: *;
  51
  52 import Memory_AXI4 :: *;
  53
  54 // ****************************************************************
  55 // ****************************************************************
  56 // Section: RTL-level interfaces
  57 // ****************************************************************
  58 // ****************************************************************
  59
  60 // ================================================================
  61 // These are the signal-level interfaces for an FlexBus master.
  62 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
  63 // we get exactly the signals specified in the FlexBus spec.
  64
  65 (* always_ready *)
  66 interface FlexBus_Master_IFC;
  67    // FlexBus External Signals
  68
  69    // AD inout bus separate for now in BSV
  70    (* result="AD"       *) interface Get#(Bit#(32))  m_AD;         // out
  71    interface Put#(Bit#(32) m_din;                                  // in
  72
  73    (* result="R_Wn"     *) interface Get#(Bit#(1))   m_R_Wn;       // out
  74    (* result="R_Wn"     *) interface Get#(Bit#(1))   m_R_Wn;       // out
  75    (* result="TSIZ"     *) interface Get#(Bit #(2)   m_TSIZ;       // out
  76
  77    (* result="FBCSn"    *) interface Get#(Bit#(6))   m_FBCSn;      // out
  78    (* result="BEn_BWEn" *) interface Get#(Bit#(4))   m_BE_BWEn;    // out
  79    (* result="TBSTn"    *) interface Get#(Bit#(1))   m_TBSTn;      // out
  80    (* result="OEn"      *) interface Get#(Bit#(1))   m_OEn;        // out
  81
  82    (* result="ALE"      *) interface Get#(Bit#(1))   m_ALE;        // out
  83    interface Put#(Bit#(1) tAn;                                     // in
  84
  85 endinterface: FlexBus_Master_IFC
  86
  87 interface FlexBus_Register_Input_IFC;
  88         method Action reset (Bit#(32) ad_bus);
  89         method Action m_ad_bus (Bit#(32) ad_bus);
  90         method Action m_data_bus (Bit#(32) data_bus);
  91 endinterface: FlexBus_Register_Input_IFC
  92
  93 interface FlexBus_Register_Output_IFC;
  94         (* always_ready, always_enabled *)   method Bit#(6) m_FBCSn();
  95         (* always_ready, always_enabled *)   method Bit#(6) m_SWS();
  96     (* always_ready, always_enabled *)   method Bit#(1) m_SWS_EN();
  97         (* always_ready, always_enabled *)   method Bit#(2) m_ASET();
  98         (* always_ready, always_enabled *)   method Bit#(2) m_RDAH();
  99         (* always_ready, always_enabled *)   method Bit#(2) m_WRAH();
 100         (* always_ready, always_enabled *)   method Bit#(6) m_WS();
 101         (* always_ready, always_enabled *)   method Bit#(1) m_AA();
 102         (* always_ready, always_enabled *)   method Bit#(2) m_PS();
 103         (* always_ready, always_enabled *)   method Bit#(1) m_BEM();
 104         (* always_ready, always_enabled *)   method Bit#(1) m_BSTR();
 105         (* always_ready, always_enabled *)   method Bit#(1) m_BSTW();
 106 endinterface: FlexBus_Register_Output_IFC
 107
 108 interface FlexBus_Register_IFC;
 109         interface FlexBus_Register_Input_IFC inp_side;
 110         interface FlexBus_Register_Output_IFC op_side;
 111 endinterface: FlexBus_Register_IFC
 112
 113 // ================================================================
 114 // These are the signal-level interfaces for an AXI4-Lite slave.
 115 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
 116 // we get exactly the signals specified in the ARM spec.
 117 (* always_ready, always_enabled    *)
 118 interface FlexBus_Slave_IFC ;
 119
 120    (* result="AD"       *) interface Put#(Bit#(32))  m_AD;         // out
 121    interface Get#(Bit#(32) m_din;                                  // in
 122
 123    (* result="R_Wn"     *) interface Put#(Bit#(1))   m_R_Wn;       // out
 124    (* result="R_Wn"     *) interface Put#(Bit#(1))   m_R_Wn;       // out
 125    (* result="TSIZ"     *) interface Put#(Bit #(2)   m_TSIZ;       // out
 126
 127    (* result="FBCSn"    *) interface Put#(Bit#(6))   m_FBCSn;      // out
 128    (* result="BEn_BWEn" *) interface Put#(Bit#(4))   m_BE_BWEn;    // out
 129    (* result="TBSTn"    *) interface Put#(Bit#(1))   m_TBSTn;      // out
 130    (* result="OEn"      *) interface Put#(Bit#(1))   m_OEn;        // out
 131
 132    (* result="ALE"      *) interface Put#(Bit#(1))   m_ALE;        // out
 133    interface Get#(Bit#(1) tAn;                                     // in
 134
 135 endinterface: FlexBus_Slave_IFC
 136
 137
 138 // ================================================================
 139 // Connecting signal-level interfaces
 140
 141 instance Connectable #(FlexBus_Master_IFC ,
 142                        FlexBus_Slave_IFC  );
 143
 144    module mkConnection #(FlexBus_Master_IFC  flexbus_m,
 145                          FlexBus_Slave_IFC  flexbus_s)
 146                        (Empty);
 147
 148     (* fire_when_enabled, no_implicit_conditions *)
 149     rule rl_flexbus_AD_signals;
 150         flexbus_s.m_AD      (flexbus_m.m_AD);
 151     endrule
 152
 153
 154       (* fire_when_enabled, no_implicit_conditions *)
 155       rule rl_flexbus_Attr_signals;
 156          flexbus_s.m_ALE     (flexbus_m.m_ALE);
 157          flexbus_s.m_R_Wn    (flexbus_m.m_R_Wn);
 158          flexbus_s.m_TSIZ    (flexbus_m.m_TSIZ);
 159       endrule
 160       (* fire_when_enabled, no_implicit_conditions *)
 161       rule rl_flexbus_signals;
 162          flexbus_s.m_FBCSn   (flexbus_m.m_FBCSn);
 163          flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
 164          flexbus_s.m_TBSTn   (flexbus_m.m_TBSTn);
 165          flexbus_s.m_OEn     (flexbus_m.m_OEn);
 166       endrule
 167       (* fire_when_enabled *)
 168       //(* fire_when_enabled, no_implicit_conditions *)
 169       rule rl_flexbus_input_signals;
 170          flexbus_m.m_din (flexbus_s.m_din);
 171          flexbus_m.m_TAn (flexbus_s.m_TAn);
 172       endrule
 173
 174    endmodule
 175 endinstance
 176
 177 // ****************************************************************
 178 // ****************************************************************
 179 // Section: Higher-level FIFO-like interfaces and transactors
 180 // ****************************************************************
 181 // ****************************************************************
 182
 183 // ================================================================
 184 // Higher-level types for payloads (rather than just bits)
 185
 186 typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
 187 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
 188 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
 189
 190 //FlexBus Addr. Data Payload
 191
 192 typedef struct {
 193    Bit #(32)     s_AD;                                     // out
 194    } FlexBus_Payload
 195 deriving (Bits, FShow);
 196
 197 typedef struct {
 198    Bit #(32)    din;                                    // in
 199    } FlexBus_din
 200 deriving (Bits, FShow);
 201
 202 //FlexBus Attributes
 203
 204 typedef struct {
 205    Bit #(1)         s_R_Wn;                                   // out
 206    Bit #(2)         s_TSIZ;                                   // out
 207    } FlexBus_Attr
 208 deriving (Bits, FShow);
 209
 210 typedef struct {
 211    Bit #(6)         s_FBCSn;                                  // out
 212    Bit #(4)         s_BEn_BWEn;                               // out
 213    Bit #(1)         s_TBSTn;                                  // out
 214    Bit #(1)         s_OEn;                                    // out
 215    } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
 216 deriving (Bits, FShow);
 217
 218 // FlexBus Control Signals
 219
 220 // Bit              s_ALE;                                    // out
 221 // Bit              s_TAn;                                    // in
 222
 223 /* ----------------------------------------------------------------
 224
 225    module mkFlexBusTop (Empty);
 226         AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
 227                                                   flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 228
 229    endmodule
 230
 231
 232 // ---------------------------------------------------------------- */
 233 // AXI4 Lite Slave to FlexBus Master transactor interface
 234
 235 interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
 236                                        numeric type wd_data,
 237                                        numeric type wd_user);
 238    method Action reset;
 239
 240    // AXI side
 241    interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
 242
 243    // FlexBus side
 244    interface FlexBus_Master_IFC flexbus_side;
 245
 246 endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
 247
 248 // ----------------------------------------------------------------
 249
 250 // AXI4 Lite Slave to FlexBus Master transactor
 251
 252 module mkAXI4_Slave_to_FlexBus_Master_Xactor
 253                 (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
 254    provisos (Add#(a__, 8, wd_addr),
 255         Add#(b__, 64, wd_data),
 256              //Bits#(Bit#(56), wd_addr),
 257              //Bits#(Bit#(64), wd_data),
 258              //Bits#(Bit#(32), wd_fb_addr),
 259              //Bits#(Bit#(32), wd_fb_data),
 260              //Bits#(Inout#(Bit#(32)), a__),
 261             // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
 262              //Bits#(Inout#(Bit#(32)), 48),
 263              Div#(wd_data, 16, 4));
 264    Bool unguarded = True;
 265    Bool guarded   = False;
 266    //let wD_FB_ADDR = valueOf(wd_fb_addr);
 267    //let wD_FB_DATA = valueOf(wd_fb_data);
 268
 269    FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
 270
 271    Reg#(Bit#(32))       r_AD            <- mkReg(0);
 272    Reg#(Bit#(32))       r_din           <- mkReg(0);
 273    Reg#(Bit#(1))        r_R_Wn          <- mkReg(1'b1);
 274    Reg#(Bit#(2))        r_TSIZ          <- mkReg(2'b00);
 275    Reg#(Bit#(6))        r_FBCSn         <- mkReg(6'h3F);
 276    Reg#(Bit#(4))        r_BE_BWEn       <- mkReg(4'hF);
 277    Reg#(Bit#(1))        r_TBSTn         <- mkReg(1'b1);
 278    Reg#(Bit#(1))        r_OEn           <- mkReg(1'b1);
 279    Reg#(Bit#(1))        r_ALE           <- mkReg(1'b0);
 280    Reg#(Bit#(1))            r_ext_TAn   <- mkReg(1'b0);
 281    Reg#(Bit#(1))            r_int_TAn   <- mkReg(1'b1);
 282
 283    Reg#(Bit#(2))        r_ASET          <- mkReg(2'b00);
 284    Reg#(Bit#(2))        r_PS            <- mkReg(2'b00);
 285    Reg#(Bit#(3))        r_rpt_cnt       <- mkReg(3'b000);
 286    Reg#(Bit#(2))        r_burst_cnt     <- mkReg(2'b00);
 287    Reg#(Bit#(2))        r_hld_cnt       <- mkReg(2'b00);
 288    Reg#(Bit#(6))        r_WS_cnt        <- mkReg(6'h00);
 289    Reg#(Bit#(6))        r_SWS_cnt       <- mkReg(6'h00);
 290    Reg#(Bit#(wd_addr))  r_awaddr    <- mkReg(0);
 291    Reg#(Bit#(2))        r_awsize    <- mkReg(0);
 292    Reg#(Bit#(wd_addr))  r2_awaddr   <- mkReg(0);
 293    Reg#(Bit#(wd_data))  r_wdata     <- mkReg(0);
 294    Reg#(AXI4_Resp)      r_wrbresp       <- mkReg(AXI4_OKAY);
 295    Reg#(AXI4_Resp)      r_rresp     <- mkReg(AXI4_OKAY);
 296    Reg#(Bit#(wd_data))  r_rd_data        <- mkReg(0);
 297    Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
 298    Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
 299    Reg#(Bit#(wd_addr))  r_araddr         <- mkReg(0);
 300    Reg#(Bit#(wd_addr))  r2_araddr        <- mkReg(0);
 301    Reg#(Bit#(2))        r_arsize         <- mkReg(0);
 302    Reg#(Bit#(4))        r_arid           <- mkReg(0);
 303    Reg#(Bit#(4))        r_awid           <- mkReg(0);
 304    Reg#(Bit#(1))        wr_pending       <- mkReg(0);
 305    Reg#(Bit#(1))        r_chk_fifos_wr   <- mkReg(0);
 306    Reg#(Bit#(1))        r_chk_fifos_rd   <- mkReg(0);
 307    ConfigReg#(Bit#(1))          rd_wrb      <- mkConfigReg(1);
 308    Reg#(Bool)           r_rready        <- mkReg(False);
 309    Reg#(Bool)           r2_rready       <- mkReg(False);
 310
 311    Reg#(Bool)           r1_awvalid      <- mkReg(False);
 312    Reg#(Bool)           r2_awvalid      <- mkReg(False);
 313    Reg#(Bool)           r1_wvalid       <- mkReg(False);
 314    Reg#(Bool)           r2_wvalid       <- mkReg(False);
 315    Reg#(Bool)               r1_arvalid  <- mkReg(False);
 316    Reg#(Bool)           r2_arvalid      <- mkReg(False);
 317
 318    Reg#(Bool)           r1_OEn          <- mkReg(True);
 319
 320    Reg#(Bit#(8))  r_AD_32bit_data_byte1  <- mkReg(0);
 321    Reg#(Bit#(8))  r_AD_32bit_data_byte2  <- mkReg(0);
 322    Reg#(Bit#(8))  r_AD_32bit_data_byte3  <- mkReg(0);
 323    Reg#(Bit#(8))  r_AD_32bit_data_byte4  <- mkReg(0);
 324
 325    Reg#(Bit#(8))  r_AD_32bit_addr_byte1  <- mkReg(0);
 326    Reg#(Bit#(8))  r_AD_32bit_addr_byte2  <- mkReg(0);
 327    Reg#(Bit#(8))  r_AD_32bit_addr_byte3  <- mkReg(0);
 328    Reg#(Bit#(8))  r_AD_32bit_addr_byte4  <- mkReg(0);
 329
 330    Reg#(Bit#(8))  r_rd_data_32bit_byte1  <- mkReg(0);
 331    Reg#(Bit#(8))  r_rd_data_32bit_byte2  <- mkReg(0);
 332    Reg#(Bit#(8))  r_rd_data_32bit_byte3  <- mkReg(0);
 333    Reg#(Bit#(8))  r_rd_data_32bit_byte4  <- mkReg(0);
 334
 335    Reg#(Bit#(32))  r_MBAR  <- mkReg(32'h04000000);
 336
 337    Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
 338    Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
 339    Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
 340
 341    // These FIFOs are guarded on BSV side, unguarded on AXI side
 342    FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
 343    FIFOF #(AXI4_Wr_Data #(wd_data))          f_wr_data <- mkGFIFOF (unguarded, unguarded);
 344    FIFOF #(AXI4_Wr_Resp #(wd_user))          f_wr_resp <- mkGFIFOF (guarded, unguarded);
 345
 346    FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
 347    FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
 348
 349    Reg#(Maybe#(Bit#(1)))  c_TAn[2] <- mkCReg(2, tagged Invalid);
 350    Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
 351
 352    //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
 353
 354    // ----------------------------------------------------------------
 355
 356    rule rl_OEn;
 357         if (r_OEn == 1'b0)
 358                 r1_OEn <= False;
 359         else
 360                 r1_OEn <= True;
 361    endrule
 362
 363    rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
 364         `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
 365         if (f_rd_addr.notEmpty) begin
 366                     register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
 367             flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
 368             `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST  r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 369         end
 370    endrule
 371
 372   (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *)
 373    rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty);
 374                 rd_wrb <= 1'b1;
 375                 r_chk_fifos_rd <= 1'b0;
 376                 r_chk_fifos_wr <= 1'b0;
 377    endrule
 378
 379    rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
 380                     if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
 381                     rd_wrb <= 1'b0;
 382                     r_chk_fifos_rd <= 1'b0;
 383                     r_chk_fifos_wr <= 1'b0;
 384             end
 385    endrule
 386
 387    rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
 388         `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
 389         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 390                     if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
 391                             f_wr_addr.deq; f_wr_data.deq;
 392                     end
 393                     else begin
 394                 flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
 395                     end
 396                     register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
 397                     register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
 398         end
 399    endrule
 400
 401    rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
 402         `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
 403         if (rd_wrb == 1'b1) begin
 404                 flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
 405                 flexbus_state_rd <= IDLE;
 406                 flexbus_state_wr <= IDLE;
 407         end
 408         else if (rd_wrb == 1'b0) begin
 409                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 410                 flexbus_state_rd <= IDLE;
 411                 flexbus_state_wr <= IDLE;
 412         end
 413         if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
 414    endrule
 415
 416    rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
 417         `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
 418         r_ASET <= register_ifc.op_side.m_ASET;
 419         Bit#(3) v_awsize = 3'b000;
 420         if ((f_wr_addr.notEmpty) )  begin
 421                 r1_awvalid <= f_wr_addr.notEmpty;
 422                 f_wr_addr.deq;
 423         r_chk_fifos_wr <= 1'b1;
 424         r_chk_fifos_rd <= 1'b1;
 425                 AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
 426                 r_awaddr <= f_wr_addr.first.awaddr;
 427                 v_awsize = f_wr_addr.first.awsize;
 428             r_awid <= f_wr_addr.first.awid;
 429                 case (v_awsize) matches
 430                         {3'b000}: r_awsize <= 2'b01;
 431                         {3'b001}: r_awsize <= 2'b10;
 432                         {3'b010}: r_awsize <= 2'b00;
 433                 endcase
 434                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
 435         end
 436         if ((f_wr_data.notEmpty) ) begin
 437                 r1_wvalid <= f_wr_data.notEmpty;
 438                 f_wr_data.deq;
 439                 `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
 440                 AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
 441                 r_wdata <= f_wr_data.first.wdata;
 442                 r1_wstrb <= f_wr_data.first.wstrb;
 443                 `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
 444         end
 445         if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
 446                 flexbus_state <= FlexBus_S1_ADDR;
 447         end
 448    endrule
 449
 450    rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
 451         `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
 452         r_ASET <= register_ifc.op_side.m_ASET;
 453         Bit#(3) v_arsize = 3'b000;
 454         if ((f_rd_addr.notEmpty) ) begin
 455                 r1_arvalid <= f_rd_addr.notEmpty;
 456                 f_rd_addr.deq;
 457         r_chk_fifos_wr <= 1'b1;
 458         r_chk_fifos_rd <= 1'b1;
 459                 AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
 460                 r_araddr <= f_rd_addr.first.araddr;
 461                 v_arsize = f_rd_addr.first.arsize;
 462             r_arid <= f_rd_addr.first.arid;
 463                 case (v_arsize) matches
 464                         {3'b000}: r_arsize <= 2'b01;
 465                         {3'b001}: r_arsize <= 2'b10;
 466                         {3'b010}: r_arsize <= 2'b00;
 467                 endcase
 468                 r_rd_data_32bit_byte1 <= 0;
 469                 r_rd_data_32bit_byte2 <= 0;
 470                 r_rd_data_32bit_byte3 <= 0;
 471                 r_rd_data_32bit_byte4 <= 0;
 472                 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
 473         end
 474         if (f_rd_addr.notEmpty) begin
 475                 flexbus_state <= FlexBus_S1_ADDR;
 476         end
 477    endrule
 478
 479    rule rl_enq_wr_resp;
 480    Bool bready = f_wr_resp.notFull;
 481    if (f_wr_resp.notFull)
 482         f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
 483                                           buser:0,
 484                                           bid:r_awid});
 485    endrule
 486
 487
 488    rule rl_enq_rd_data;
 489         Bool rready = f_rd_data.notFull;
 490         if (f_rd_data.notFull && r2_rready) begin
 491                 f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
 492                                                   rresp: r_rresp,
 493                                                   rlast: True,
 494                                                   ruser:0,
 495                           rid:r_arid});
 496                 //AXI4_Slave_IFC.m_rready(True);
 497                 `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
 498         end
 499    endrule
 500
 501    rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
 502         `ifdef verbose_debug $display("STATE S1 FIRED");`endif
 503         r_PS   <= register_ifc.op_side.m_PS;
 504         r_WS_cnt <= register_ifc.op_side.m_WS;
 505         r_OEn <= 1'b1;
 506         r_BE_BWEn <= 4'hF;
 507         r_FBCSn <= 6'h3F;
 508         r_ALE <= 1'b1;
 509         `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
 510                 if (r_rpt_cnt == 3'b000) begin
 511                         if (r1_arvalid) begin
 512                                 r_AD <= r_araddr[31:0];
 513                                 r_R_Wn <= 1'b1;   // Read
 514                                 r_TSIZ <= r_arsize;
 515                         end
 516                         else if (r1_awvalid && r1_wvalid) begin
 517                                 r_AD <= r_awaddr[31:0];
 518                                 r_R_Wn <= 1'b0;   // WriteBar
 519                                 r_TSIZ <= r_awsize;
 520                         end
 521                 end
 522                 else begin
 523                         if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
 524                         else r_AD <= r_araddr[31:0];
 525                         r_TBSTn <= 1'b1;
 526                         r_TSIZ <= register_ifc.op_side.m_PS;
 527                 end
 528         if (( r_ASET != 2'b00) ) begin
 529                 r_ASET <= r_ASET - 1;
 530         end
 531         else begin
 532                 flexbus_state <= FlexBus_S2_WRITE;
 533                 if (r_rpt_cnt != 3'b000)
 534                         r_rpt_cnt <= r_rpt_cnt -1;
 535         end
 536    endrule
 537
 538    rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
 539         `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
 540
 541         r2_awvalid <= r1_awvalid;
 542         r2_wvalid  <= r1_wvalid;
 543         r2_wstrb   <= r1_wstrb;
 544         r2_arvalid <= r1_arvalid;
 545
 546         r2_araddr <= r_araddr;
 547         r2_awaddr <= r_awaddr;
 548
 549         r_AD_32bit_data_byte1   <= pack(r_wdata[7:0]);
 550         r_AD_32bit_data_byte2   <= pack(r_wdata[15:8]);
 551         r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]);
 552         r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
 553         r_AD_32bit_addr_byte1  <= pack(r_awaddr[31:24]);
 554         r_AD_32bit_addr_byte2  <= pack(r_awaddr[23:16]);
 555         r_AD_32bit_addr_byte3  <= pack(r_awaddr[15:8]);
 556         r_AD_32bit_addr_byte4  <= pack(r_awaddr[7:0]);
 557         `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
 558         $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
 559    endrule
 560
 561    rule rl_assign_rd_data;
 562         r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
 563         r2_rready <= r_rready;
 564         `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
 565    endrule
 566
 567    rule rl_read_ext_signals;
 568         if (isValid(c_TAn[1])) begin
 569                 r_ext_TAn <= fromMaybe(?,c_TAn[1]);
 570                 c_TAn[1]<= tagged Invalid;
 571         end
 572         if (isValid(c_din[1])) begin
 573                 r_din <= fromMaybe(?,c_din[1]);
 574                 c_din[1]<= tagged Invalid;
 575         end
 576     //r_din <= tri_AD_out._read;
 577    endrule
 578
 579    rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
 580         `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
 581         r_ALE <= 1'b0;
 582         r_FBCSn <= register_ifc.op_side.m_FBCSn;
 583         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 584         if (r_R_Wn == 1'b1)
 585                 r_hld_cnt <= register_ifc.op_side.m_RDAH;
 586         else
 587                 r_hld_cnt <= register_ifc.op_side.m_WRAH;
 588                    if (r_R_Wn == 1'b1) begin
 589                         r_OEn <= 1'b0;
 590                         if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 591                                 r_TBSTn <= 1'b0;
 592                         end
 593                    end
 594                    else begin
 595                         // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
 596                         if ((r_rpt_cnt == 3'b000) ) begin
 597                                 if (r_PS == 2'b01) begin
 598                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 599                                 end
 600                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 601                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 602                                 end
 603                                 else begin
 604                                         r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 605                                 end
 606                         end
 607                         else if (r_rpt_cnt == 3'b011) begin
 608                                         r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 609                         end
 610                         else if (r_rpt_cnt == 3'b010)
 611                                         r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 612                         else if  (r_rpt_cnt == 3'b001) begin
 613                                 if (r_awsize == 2'b00) begin
 614                                         if ((r_PS == 2'b10) || (r_PS == 2'b11))
 615                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 616                                         else if ((r_PS == 2'b01))
 617                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 618                                         end
 619                                 else if (r_awsize == 2'b10) begin
 620                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 621
 622                                 end
 623                         end
 624                         if (register_ifc.op_side.m_BEM == 1'b1)
 625                                 r_BE_BWEn <= r2_wstrb[3:0];
 626                         if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 627                                 r_TBSTn <= 1'b0;
 628                         end
 629                    end
 630                 if (r_WS_cnt == 6'h00) begin
 631                     if (r_ext_TAn == 1'b0) begin
 632                         //r_int_TAn <= 1'b0;
 633                         flexbus_state <= FlexBus_S3_BURST;
 634                     end
 635                     if (register_ifc.op_side.m_AA == 1'b1) begin
 636                         r_int_TAn <= 1'b1;
 637                     end
 638                     r_WS_cnt <= register_ifc.op_side.m_WS;
 639                     if (r_R_Wn == 1'b1) begin
 640                         if (r_arsize == 2'b00) begin
 641                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 642                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 643                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 644                                 end
 645                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 646                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 647                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 648                                 end
 649                         end
 650                         else if (r_arsize == 2'b10) begin
 651                                 if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
 652                                         r_burst_cnt <= 2'b01;
 653                                 end
 654                                 else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
 655                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 656                                 end
 657                         end
 658                    end
 659                    else begin
 660                         if (r_awsize == 2'b00) begin
 661                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 662                                         if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
 663                                         if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
 664                                 end
 665                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
 666                                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
 667                                         if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 668                                 end
 669                         end
 670                         else if (r_awsize == 2'b10) begin
 671                                 if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
 672                                         r_burst_cnt <= 2'b01;
 673                                 end
 674                                 else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
 675                                         if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
 676                                 end
 677                         end
 678                    end
 679                 end
 680                 else begin
 681                    r_WS_cnt <= r_WS_cnt -1;
 682              end
 683              `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
 684    endrule
 685
 686    rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
 687         `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
 688         `ifdef verbose_debug_l2
 689         $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
 690         $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
 691         $display (" r_AD in BURST = %h", r_AD);
 692         $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
 693         `endif
 694         if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
 695                 flexbus_state <= FlexBus_S4_HOLD;
 696                 if (r_R_Wn == 1'b1) begin
 697                 r_rresp <= AXI4_SLVERR; //SLVERR
 698         end else begin
 699                 r_wrbresp <= AXI4_SLVERR; //SLVERR
 700         end
 701         end
 702         else if (r_rpt_cnt == 3'b001) begin
 703                 if (r_R_Wn == 1'b1) begin
 704                         if (r_arsize == 2'b00) begin
 705                                 if (r_PS == 2'b01) begin
 706                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 707                                 end
 708                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 709                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 710                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 711                                 end
 712                         end
 713                         else if (r_arsize == 2'b10) begin
 714                                 if (r_PS == 2'b01)
 715                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 716                         end
 717                         r_rready <= True;
 718                         //r_rpt_cnt <= r_rpt_cnt -1;
 719                 end
 720                 //else
 721                 flexbus_state <= FlexBus_S4_HOLD;
 722                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 723                         r_OEn <= 1'b1;
 724                         r_BE_BWEn <= 4'hF;
 725                         r_FBCSn <= 6'h3F;
 726                 end
 727         end
 728         else if (r_rpt_cnt != 3'b000) begin
 729                 flexbus_state <= FlexBus_S1_ADDR;
 730                 r_ASET <= register_ifc.op_side.m_ASET;
 731                 if (register_ifc.op_side.m_AA == 1'b1) begin
 732                         r_OEn <= 1'b1;
 733                         r_BE_BWEn <= 4'hF;
 734                         r_FBCSn <= 6'h3F;
 735                 end
 736                 if (r_R_Wn == 1'b1) begin
 737                         if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
 738                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 739                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
 740                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 741                         else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
 742                                 if (r_arsize == 2'b00)
 743                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 744                                 else if (r_arsize == 2'b10)
 745                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 746                         end
 747                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 748                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 749                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 750                         end
 751                 end
 752         end
 753         else if (r_burst_cnt == 2'b01) begin
 754                 if (r_ext_TAn == 1'b1) begin
 755                         flexbus_state <= FlexBus_S4_HOLD;
 756                 end
 757                 else begin
 758                         if (r_R_Wn == 1'b0) begin
 759                                 if (r_awsize == 2'b00) begin
 760                                         if (r_PS == 2'b01)
 761                                                 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 762                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 763                                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 764                                         //else
 765                                         //      r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
 766                                 end
 767                                 else if (r_awsize == 2'b10) begin
 768                                         if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 769                                 end
 770                         end
 771                         else begin
 772                                 if (r_arsize == 2'b00) begin
 773                                         if (r_PS == 2'b01)
 774                                                 r_rd_data_32bit_byte3 <= r_din[7:0];
 775                                         else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 776                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 777                                                 r_rd_data_32bit_byte2 <= r_din[15:8];
 778                                         end
 779                                 end
 780                                 else if (r_arsize == 2'b10) begin
 781                                         if (r_PS == 2'b01)
 782                                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 783                                 end
 784                         end
 785                         if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 786                                 if (r_SWS_cnt == 6'h00) begin
 787                                         r_SWS_cnt <= register_ifc.op_side.m_SWS;
 788                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 789                                                 r_int_TAn <= 1'b1;
 790                                                 r_OEn <= 1'b1;
 791                                                 r_BE_BWEn <= 4'hF;
 792                                                 r_FBCSn <= 6'h3F;
 793                                         end
 794                                         r_burst_cnt <= r_burst_cnt -1;
 795                                         //flexbus_state <= FlexBus_S4_HOLD;
 796                                 end
 797                                 else begin
 798                                         r_SWS_cnt <= r_SWS_cnt -1;
 799                                 end
 800                         end
 801                         else begin
 802                                 if (r_WS_cnt == 6'h00) begin
 803                                         r_WS_cnt <= register_ifc.op_side.m_WS;
 804                                         if (register_ifc.op_side.m_AA == 1'b1) begin
 805                                                 r_int_TAn <= 1'b1;
 806                                                 r_OEn <= 1'b1;
 807                                                 r_BE_BWEn <= 4'hF;
 808                                                 r_FBCSn <= 6'h3F;
 809                                         end
 810                                         r_burst_cnt <= r_burst_cnt -1;
 811                                         //flexbus_state <= FlexBus_S4_HOLD;
 812                                 end
 813                                 else
 814                                         r_WS_cnt <= r_WS_cnt - 1;
 815                         end
 816                 end
 817         end
 818         else if (r_burst_cnt != 2'b00) begin
 819                 if (r_R_Wn == 1'b0) begin
 820                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 821                                 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 822                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 823                                 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 824                         end
 825                         //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01))
 826                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 827                         //else if ((r_PS == 2'b10) || (r_PS == 2'b11))
 828                         //      r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
 829                 end
 830                 else begin
 831                         if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
 832                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 833                         else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
 834                                 r_rd_data_32bit_byte2 <= r_din[7:0];
 835                         end
 836                 end
 837                 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
 838                         if (r_SWS_cnt == 6'h00) begin
 839                                 r_SWS_cnt <= register_ifc.op_side.m_SWS;
 840                                 if (register_ifc.op_side.m_AA == 1'b1)
 841                                         r_int_TAn <= 1'b1;
 842                                 r_burst_cnt <= r_burst_cnt -1;
 843                         end
 844                         else begin
 845                                 r_SWS_cnt <= r_SWS_cnt -1;
 846                         end
 847                 end
 848                 else begin
 849                         if (r_WS_cnt == 6'h00) begin
 850                                 r_WS_cnt <= register_ifc.op_side.m_WS;
 851                                 if (register_ifc.op_side.m_AA == 1'b1)
 852                                         r_int_TAn <= 1'b1;
 853                                 r_burst_cnt <= r_burst_cnt -1;
 854                         end
 855                         else begin
 856                                 r_WS_cnt <= r_WS_cnt - 1;
 857                         end
 858                end
 859         end
 860         else if (r_burst_cnt == 2'b00) begin
 861                 flexbus_state <= FlexBus_S4_HOLD;
 862                 if (r_R_Wn == 1'b1) begin
 863                         if (r_arsize == 2'b00) begin
 864                                 if (r_PS == 2'b01) begin
 865                                         r_rd_data_32bit_byte4 <= r_din[7:0];
 866                                 end
 867                                 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 868                                         r_rd_data_32bit_byte3 <= r_din[7:0];
 869                                         r_rd_data_32bit_byte4 <= r_din[15:8];
 870                                 end
 871                                 else begin
 872                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 873                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 874                                         r_rd_data_32bit_byte3 <= r_din[23:16];
 875                                         r_rd_data_32bit_byte4 <= r_din[31:24];
 876                                 end
 877                         end
 878                         else if (r_arsize == 2'b10) begin
 879                                 if (r_PS == 2'b01)
 880                                         r_rd_data_32bit_byte2 <= r_din[7:0];
 881                                 //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
 882                                 else begin
 883                                         r_rd_data_32bit_byte1 <= r_din[7:0];
 884                                         r_rd_data_32bit_byte2 <= r_din[15:8];
 885                                 end
 886                         end
 887                         else if (r_arsize == 2'b01) begin
 888                                 r_rd_data_32bit_byte1 <= r_din[7:0];
 889                         end
 890                         r_rready <= True;
 891                 end
 892                 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality  later for now
 893                         r_OEn <= 1'b1;
 894                         r_BE_BWEn <= 4'hF;
 895                         r_FBCSn <= 6'h3F;
 896                 end
 897         end
 898    endrule
 899
 900    rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
 901         `ifdef verbose_debug $display("STATE S4 FIRED");`endif
 902         r_int_TAn <= 1'b1;
 903         r_R_Wn <= 1'b1;
 904         r_OEn <= 1'b1;
 905         r_BE_BWEn <= 4'hF;
 906         r_FBCSn <= 6'h3F;
 907         r_TBSTn <= 1'b1;
 908         if (r_hld_cnt ==  2'b00) begin
 909             if (wr_pending == 1'b1) begin
 910                 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
 911                     flexbus_state_wr <= IDLE;
 912                     flexbus_state_rd <= IDLE;
 913                 wr_pending <= 1'b0;
 914             end
 915             else begin
 916                 flexbus_state <= IDLE;
 917                     flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
 918                     flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
 919             end
 920                 r1_arvalid  <= False;
 921                 r1_awvalid  <= False;
 922                 r1_wvalid   <= False;
 923
 924                         r_rready        <= False;
 925                 r_wrbresp       <= AXI4_OKAY;
 926                 r_rresp     <= AXI4_OKAY;
 927                 r_ASET          <= 2'b00;
 928                 r_rpt_cnt       <= 3'b000;
 929                 r_burst_cnt     <= 2'b00;
 930                 r_hld_cnt       <= 2'b00;
 931                 r_WS_cnt        <= 6'h00;
 932                 r_SWS_cnt       <= 6'h00;
 933                 r_awaddr        <= 0;
 934                 r_wdata         <= 0;
 935                 //r_rd_data     <= 0;
 936                 r1_wstrb        <= 0;
 937                 //r2_wstrb      <= 0;
 938                 r_araddr        <= 0;
 939         end
 940         else
 941                 r_hld_cnt <= r_hld_cnt -1;
 942    endrule
 943
 944    // ----------------------------------------------------------------
 945    // INTERFACE
 946
 947    method Action reset;
 948       `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
 949       f_wr_addr.clear;
 950       f_wr_data.clear;
 951       f_wr_resp.clear;
 952       f_rd_addr.clear;
 953       f_rd_data.clear;
 954
 955       c_TAn[0]<= tagged Invalid;
 956       c_din[0]<= tagged Invalid;
 957    endmethod
 958
 959    // AXI side
 960    interface axi_side = interface AXI4_Slave_IFC;
 961
 962                            // Wr Addr channel
 963                            method Action m_awvalid (Bool           awvalid,
 964                                                     Bit #(wd_addr) awaddr,
 965                                                                 Bit#(3) awsize,
 966                                                     Bit #(wd_user) awuser,
 967                                                                 Bit#(8) awlen,
 968                                                                 Bit#(2) awburst,
 969                                 Bit#(4) awid
 970                                                                 );
 971                   if (awvalid && f_wr_addr.notFull) begin
 972                                         f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
 973                                                                    awuser: awuser,
 974                                                                          awlen:awlen,
 975                                                                          awsize:awsize,
 976                                                                          awburst:awburst,
 977                                      awid:awid});
 978                     end
 979                            endmethod
 980
 981                            method Bool m_awready;
 982                               return f_wr_addr.notFull;
 983                            endmethod
 984
 985                            // Wr Data channel
 986                            method Action m_wvalid (Bool                      wvalid,
 987                                                    Bit #(wd_data)            wdata,
 988                                                    Bit #(TDiv #(wd_data, 8)) wstrb,
 989                                                          Bool wlast,
 990                                                          Bit#(4) wid);
 991                              if (wvalid && f_wr_data.notFull) begin
 992                                  f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
 993                             end
 994                            endmethod
 995
 996                            method Bool m_wready;
 997                               return f_wr_data.notFull;
 998                            endmethod
 999
1000                            // Wr Response channel
1001                            method Bool           m_bvalid = f_wr_resp.notEmpty;
1002                            method Bit #(2)       m_bresp  = pack (f_wr_resp.first.bresp);
1003                            method Bit #(wd_user) m_buser  = f_wr_resp.first.buser;
1004                            method Bit #(4)       m_bid  = f_wr_resp.first.bid;
1005                            method Action m_bready (Bool bready);
1006                               if (bready && f_wr_resp.notEmpty)
1007                                  f_wr_resp.deq;
1008                            endmethod
1009
1010                            // Rd Addr channel
1011                            method Action m_arvalid (Bool           arvalid,
1012                                                     Bit #(wd_addr) araddr,
1013                                                                 Bit#(3)                          arsize,
1014                                                     Bit #(wd_user) aruser,
1015                                                                 Bit#(8)                          arlen,
1016                                                                 Bit#(2)                          arburst,
1017                                 Bit#(4) arid);
1018                                 if (arvalid && f_rd_addr.notFull) begin
1019                                  f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
1020                                                                    aruser: aruser,
1021                                                                          arlen : arlen,
1022                                                                          arsize: arsize,
1023                                                                          arburst:arburst,
1024                                      arid:arid});
1025                         end
1026                            endmethod
1027
1028                            method Bool m_arready;
1029                               return f_rd_addr.notFull;
1030                            endmethod
1031
1032                            // Rd Data channel
1033                            method Bool           m_rvalid = f_rd_data.notEmpty;
1034                            method Bit #(2)       m_rresp  = pack (f_rd_data.first.rresp);
1035                            method Bit #(wd_data) m_rdata  = f_rd_data.first.rdata;
1036                            method Bool m_rlast  = f_rd_data.first.rlast;
1037                            method Bit #(wd_user) m_ruser  = f_rd_data.first.ruser;
1038                            method Bit#(4) m_rid=f_rd_data.first.rid;
1039
1040                            method Action m_rready (Bool rready);
1041                               if (rready && f_rd_data.notEmpty)
1042                                  f_rd_data.deq;
1043                            endmethod
1044                         endinterface;
1045
1046 interface flexbus_side = interface FlexBus_Master_IFC;
1047             //interface io_AD_master = tri_AD_out.io;
1048
1049     interface c_TAn = interface Put
1050         method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
1051             c_TAn[0] <= tagged Valid in;
1052         endmethod
1053     endinterface;
1054
1055     interface m_din = interface Put
1056         method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
1057             c_din[0] <= tagged Valid in;
1058         endmethod
1059     endinterface;
1060
1061     interface m_AD = interface Get
1062         method ActionValue#(Bit#(32)) get;
1063             return r_AD;
1064         endmethod
1065     endinterface;
1066
1067     interface m_R_Wn = interface Get
1068         method ActionValue#(Bit#(1)) get;
1069             return r_R_Wn;
1070         endmethod
1071     endinterface;
1072
1073     interface m_TSIZ = interface Get
1074         method ActionValue#(Bit#(2)) get;
1075             return r_TSIZ;
1076         endmethod
1077     endinterface;
1078
1079     interface m_FBCSn = interface Get
1080         method ActionValue#(Bit#(6)) get;
1081             return r_FBCSn;
1082         endmethod
1083     endinterface;
1084
1085     interface m_BE_BWEn = interface Get
1086         method ActionValue#(Bit#(4)) get;
1087             return r_BE_BWEn;
1088         endmethod
1089     endinterface;
1090
1091     interface m_TBSTn = interface Get
1092         method ActionValue#(Bit#(1)) get;
1093             return r_TBSTn;
1094         endmethod
1095     endinterface;
1096
1097     interface m_OEn = interface Get
1098         method ActionValue#(Bit#(1)) get;
1099             return r_OEn;
1100         endmethod
1101     endinterface;
1102
1103     interface m_ALE = interface Get
1104         method ActionValue#(Bit#(1)) get;
1105             return r_ALE;
1106         endmethod
1107     endinterface;
1108
1109     //endinterface;
1110
1111 endinterface;
1112
1113 endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
1114
1115 module mkFlexBus_Registers (FlexBus_Register_IFC);
1116
1117 // Vectors of Chip Select AR, MR and Control Registers
1118         Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
1119         Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
1120         Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
1121
1122 // Control Register Fields
1123
1124         Reg#(Bit#(6)) r_FBCSn   <- mkReg(6'h3F);
1125         Reg#(Bit#(6)) r_SWS     <- mkReg(6'h00);
1126         Reg#(Bit#(1)) r_SWS_EN  <- mkReg(1'b0);
1127         Reg#(Bit#(2)) r_ASET    <- mkReg(2'b00);
1128         Reg#(Bit#(2)) r_RDAH    <- mkReg(2'b00);
1129         Reg#(Bit#(2)) r_WRAH    <- mkReg(2'b00);
1130         Reg#(Bit#(6)) r_WS      <- mkReg(6'h00);
1131         Reg#(Bit#(1)) r_AA      <- mkReg(1'b0);
1132         Reg#(Bit#(2)) r_PS      <- mkReg(2'b00);
1133         Reg#(Bit#(1)) r_BEM     <- mkReg(1'b0);
1134         Reg#(Bit#(1)) r_BSTR    <- mkReg(1'b0);
1135         Reg#(Bit#(1)) r_BSTW    <- mkReg(1'b0);
1136
1137         Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
1138         Reg#(Bit#(32)) r_ad_bus         <- mkReg(32'hFFFFFFFF);
1139         Reg#(Bit#(32)) r_data_bus       <- mkReg(32'h00000000);
1140         Reg#(Bit#(32)) r_MBAR           <- mkReg(32'h04000000);
1141 //------------------------------------------------------------------------
1142
1143         rule rl_write_config_regs;
1144                 Bit#(32) v_MBAR = r_MBAR + 'h0500;
1145                 for (int i=0; i<6; i=i+1) begin
1146                         if ( v_MBAR == r_ad_bus) begin
1147                                 vec_addr_regs[i][31:16] <= r_data_bus[31:16];
1148                         end
1149                         v_MBAR = v_MBAR + 'h04;
1150                         if ( v_MBAR == r_ad_bus) begin
1151                                 vec_mask_regs[i] <= r_data_bus;
1152                         end
1153                         v_MBAR = v_MBAR + 'h04;
1154                         if ( v_MBAR == r_ad_bus) begin
1155                                 vec_cntr_regs[i] <= r_data_bus;
1156                         end
1157                         v_MBAR = v_MBAR + 'h04;
1158                 end
1159         endrule
1160
1161         rule rl_generate_individual_chip_sels;
1162
1163            Bit#(6) chp_sel_vec = 6'h3F;
1164            Bit#(32) r_cntr_reg_sel = 32'h00000000;
1165            for (int i=0; i<6; i=i+1) begin
1166                 if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
1167                         chp_sel_vec[i] = 1'b0;
1168                 end
1169            end
1170            r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
1171
1172                 case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
1173                     {6'b111110}: r_cntr_reg_sel   = vec_cntr_regs[0];
1174                     {6'b111101}: r_cntr_reg_sel   = vec_cntr_regs[1];
1175                     {6'b111011}: r_cntr_reg_sel   = vec_cntr_regs[2];
1176                     {6'b110111}: r_cntr_reg_sel   = vec_cntr_regs[3];
1177                     {6'b101111}: r_cntr_reg_sel   = vec_cntr_regs[4];
1178                     {6'b011111}: r_cntr_reg_sel   = vec_cntr_regs[5];
1179                 endcase
1180
1181                 r_SWS           <= r_cntr_reg_sel[31:26];
1182                 r_SWS_EN        <= r_cntr_reg_sel[23];
1183                 r_ASET          <= r_cntr_reg_sel[21:20];
1184                 r_RDAH          <= r_cntr_reg_sel[19:18];
1185                 r_WRAH          <= r_cntr_reg_sel[17:16];
1186                 //r_WS                  <= r_cntr_reg_sel[15:10];
1187         r_WS        <= 6'h06;
1188                 r_AA            <= r_cntr_reg_sel[8];
1189                 r_PS            <= r_cntr_reg_sel[7:6];
1190                 r_BEM           <= r_cntr_reg_sel[5];
1191                 r_BSTR          <= r_cntr_reg_sel[4];
1192                 r_BSTW          <= r_cntr_reg_sel[3];
1193         endrule
1194 //-------------------------------------------------------------------------
1195 // FlexBus Register Input Interface
1196 interface inp_side = interface FlexBus_Register_Input_IFC;
1197         method Action reset (Bit #(32) ad_bus);
1198                 for (int i=0; i<6; i=i+1)
1199                     vec_addr_regs[i] <= 32'h00000000;
1200                 for (int i=0; i<6; i=i+1)
1201                     vec_mask_regs[i] <= 32'h00000000;
1202                 for (int i=0; i<6; i=i+1)
1203                     vec_cntr_regs[i] <= 32'h00000000;
1204                 r_rom_cntr_reg_0[8] <= ad_bus[2];
1205                 r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
1206                 r_rom_cntr_reg_0[5] <= ad_bus[3];
1207                 r_rom_cntr_reg_0[15:10] <= 6'h3F;
1208                 r_rom_cntr_reg_0[21:16] <= 6'h3F;
1209                 vec_cntr_regs[0] <= r_rom_cntr_reg_0;
1210         endmethod
1211         method Action m_ad_bus (Bit #(32) ad_bus);
1212                 r_ad_bus <= ad_bus;
1213         endmethod
1214         method Action m_data_bus (Bit #(32) data_bus);
1215                 r_data_bus <= data_bus;
1216         endmethod
1217         endinterface;
1218
1219 // FlexBus Register Output Interface
1220 interface op_side = interface FlexBus_Register_Output_IFC;
1221         method Bit#(6) m_FBCSn ();
1222                return r_FBCSn;
1223         endmethod
1224         method Bit#(6) m_SWS ();
1225                return r_SWS;
1226         endmethod
1227         method Bit#(1) m_SWS_EN ();
1228                return r_SWS_EN;
1229         endmethod
1230         method Bit#(2) m_ASET ();
1231                return r_ASET;
1232         endmethod
1233         method Bit#(2) m_RDAH ();
1234                return r_RDAH;
1235         endmethod
1236         method Bit#(2) m_WRAH ();
1237                return r_WRAH;
1238         endmethod
1239         method Bit#(6) m_WS ();
1240                return r_WS;
1241         endmethod
1242         method Bit#(1) m_AA ();
1243                return r_AA;
1244         endmethod
1245         method Bit#(2) m_PS ();
1246                return r_PS;
1247         endmethod
1248         method Bit#(1) m_BEM ();
1249                return r_BEM;
1250         endmethod
1251         method Bit#(1) m_BSTR ();
1252                return r_BSTR;
1253         endmethod
1254         method Bit#(1) m_BSTW ();
1255                return r_BSTW;
1256         endmethod
1257         endinterface;
1258
1259 endmodule: mkFlexBus_Registers
1260
1261
1262 endpackage