projects / shakti-peripherals.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
tdo_oe is actually tms
[shakti-peripherals.git] / src / peripherals / jtagdtm / jtagdtm.bsv
1 /*
2 Copyright (c) 2013, IIT Madras
3 All rights reserved.
4
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
13 */
14 package jtagdtm;
15 /*====== Package imports ======= */
16 import Clocks::*;
17 import ConcatReg::*;
18 import GetPut::*;
19 import FIFO::*;
20 import FIFOF::*;
21 import SpecialFIFOs::*;
22 import DReg::*;
23 /*======= Project imports ===== */
24 `include "jtagdefines.bsv"
25 //import defined_types::*;
26 /*============================== */
27
28 interface Ifc_jtagdtm;
29 /*======== Scan input pins ===== */
30 (*always_enabled,always_ready*)
31 method Action scan_out_1_i(Bit#(1) scan_out_1);
32 (*always_enabled,always_ready*)
33 method Action scan_out_2_i(Bit#(1) scan_out_2);
34 (*always_enabled,always_ready*)
35 method Action scan_out_3_i(Bit#(1) scan_out_3);
36 (*always_enabled,always_ready*)
37 method Action scan_out_4_i(Bit#(1) scan_out_4);
38 (*always_enabled,always_ready*)
39 method Action scan_out_5_i(Bit#(1) scan_out_5);
40 /*======= SCAN Output Pins ====== */
41 (*always_enabled,always_ready*)
42 method Bit#(1) scan_in_1;
43 (*always_enabled,always_ready*)
44 method Bit#(1) scan_in_2;
45 (*always_enabled,always_ready*)
46 method Bit#(1) scan_in_3;
47 (*always_enabled,always_ready*)
48 method Bit#(1) scan_in_4;
49 (*always_enabled,always_ready*)
50 method Bit#(1) scan_in_5;
51 (*always_enabled,always_ready*)
52 method Bit#(1) scan_en;
53 (*always_enabled,always_ready*)
54 method Bit#(1) scan_mode_te;
55 /*======= BOUNDARY SCAN Output Pin ====== */
56 (*always_enabled,always_ready*)
57 method Action bs_chain_i(Bit#(1) bs_chain);
58 /*======= BOUNDARY SCAN input Pins ====== */
59 (*always_enabled,always_ready*)
60 method Bit#(1) shiftBscan2Edge;
61 (*always_enabled,always_ready*)
62 method Bit#(1) selectJtagInput;
63 (*always_enabled,always_ready*)
64 method Bit#(1) selectJtagOutput;
65 (*always_enabled,always_ready*)
66 method Bit#(1) updateBscan;
67 (*always_enabled,always_ready*)
68 method Bit#(1) bscan_in;
69 (*always_enabled,always_ready*)
70 method Bit#(1) scan_shift_en;
71 /*======== JTAG input pins ===== */
72 (*always_enabled,always_ready*)
73 interface Put#(Bit#(1)) tms;
74 (*always_enabled,always_ready*)
75 interface Put#(Bit#(1)) tdi;
76 /*==== inputs from Sub-modules === */
77 method Action debug_tdi_i(Bit#(1) debug_tdi);
78 /*======= JTAG Output Pins ====== */
79 (*always_enabled,always_ready*)
80 interface Get#(Bit#(1)) tdo;
81 (*always_enabled,always_ready*)
82 interface Get#(Bit#(1)) tck;
83
84 /*======== TAP States ============= */
85 method Bit#(1) shift_dr;
86 method Bit#(1) pause_dr;
87 method Bit#(1) update_dr;
88 method Bit#(1) capture_dr;
89 /*=========== Output for BS Chain ==== */
90 method Bit#(1) extest_select;
91 method Bit#(1) sample_preload_select;
92 method Bit#(1) debug_select;
93 method Bit#(1) debug_tdo;
94 /*================================ */
95 method Action response_from_dm(Bit#(34) responsedm);
96 method ActionValue#(Bit#(40)) request_to_dm;
97
98 endinterface
99
100 function Reg#(t) readOnlyReg(t r);
101 return (interface Reg;
102 method t _read = r;
103 method Action _write(t x) = noAction;
104 endinterface);
105 endfunction
106 function Reg#(Bit#(1)) condwriteSideEffect(Reg#(Bit#(1)) r, Action a);
107 return (interface Reg;
108 method Bit#(1) _read = r._read;
109 method Action _write(Bit#(1) x);
110 r._write(x);
111 if(x==1)
112 a;
113 endmethod
114 endinterface);
115 endfunction
116
117
118
119 typedef enum {TestLogicReset = 4'h0, RunTestIdle = 4'h1, SelectDRScan = 4'h2,
120 CaptureDR = 4'h3, ShiftDR = 4'h4, Exit1DR = 4'h5,
121 PauseDR = 4'h6, Exit2DR = 4'h7, UpdateDR = 4'h8,
122 SelectIRScan = 4'h9, CaptureIR = 4'ha, ShiftIR = 4'hb,
123 Exit1IR = 4'hc, PauseIR = 4'hd, Exit2IR = 4'he,
124 UpdateIR = 4'hf } TapStates deriving(Bits,Eq,FShow);
125
126 (*synthesize*)
127 (*descending_urgency="scan_logic,scan_shift_en"*)
128 module mkjtagdtm(Ifc_jtagdtm);
129 Clock def_clk<-exposeCurrentClock;
130 Clock invert_clock<-invertCurrentClock;
131 Reset invert_reset<-mkAsyncResetFromCR(0,invert_clock);
132
133 /*========= FIFOs to communicate with the DM==== */
134 FIFOF#(Bit#(40)) request_to_DM <-mkUGFIFOF1();
135 FIFOF#(Bit#(34)) response_from_DM <-mkUGFIFOF1();
136 /*================================================ */
137
138 /*=== Wires to capture the input pins === */
139 Wire#(Bit#(1)) wr_tms<-mkDWire(0);
140 Wire#(Bit#(1)) wr_tdi<-mkDWire(0);
141 Reg#(Bit#(1)) wr_debug_tdi<-mkRegA(0);
142 Reg#(Bit#(1)) wr_bs_chain_tdo<-mkRegA(0);
143 /*======================================== */
144
145 Wire#(Bit#(1)) wr_scan_in_1_all <-mkDWire(0);
146 Wire#(Bit#(1)) wr_scan_in_2_out1 <-mkDWire(0);
147 Wire#(Bit#(1)) wr_scan_in_3_out2 <-mkDWire(0);
148 Wire#(Bit#(1)) wr_scan_in_4_out3 <-mkDWire(0);
149 Wire#(Bit#(1)) wr_scan_in_5_out4 <-mkDWire(0);
150 Reg#(Bit#(1)) wr_scan_shift_en[2] <-mkCRegA(2,0);
151
152 Reg#(TapStates) tapstate<-mkRegA(TestLogicReset);
153 Reg#(Bit#(5)) instruction_shiftreg<-mkRegA(0);
154 Reg#(Bit#(5)) instruction<-mkRegA(`IDCODE, clocked_by invert_clock, reset_by invert_reset); // clock this by the inverted clock
155 Reg#(Bit#(1)) bypass_sr<-mkRegA(0);
156 Reg#(Bit#(1)) scan1_sr <-mkRegA(0);
157 Reg#(Bit#(1)) scan2_sr <-mkRegA(0);
158 Reg#(Bit#(1)) scan3_sr <-mkRegA(0);
159 Reg#(Bit#(1)) scan4_sr <-mkRegA(0);
160 Reg#(Bit#(1)) scan5_sr <-mkRegA(0);
161 Reg#(Bit#(1)) scanall_sr<-mkRegA(0);
162 Reg#(Bit#(1)) scan_en_sr<-mkRegA(0);
163 Reg#(Bit#(1)) scan_mode_te_sr<-mkRegA(0);
164 Reg#(Bit#(1)) full_scan_en_sr<-mkRegA(0);
165 Reg#(Bit#(1)) scan_out_1_sr<-mkRegA(0);
166 Reg#(Bit#(1)) scan_out_2_sr<-mkRegA(0);
167 Reg#(Bit#(1)) scan_out_3_sr<-mkRegA(0);
168 Reg#(Bit#(1)) scan_out_4_sr<-mkRegA(0);
169 Reg#(Bit#(1)) scan_out_5_sr<-mkRegA(0);
170 Wire#(Bit#(1)) shiftBscan2Edge_sr<-mkDWire(0);
171 Wire#(Bit#(1)) selectJtagInput_sr<-mkDWire(0);
172 Wire#(Bit#(1)) selectJtagOutput_sr<-mkDWire(0);
173 Wire#(Bit#(1)) updateBscan_sr<-mkDWire(0);
174 Reg#(Bit#(1)) bs_sr<-mkRegA(0);
175 Reg#(Bit#(32)) idcode_sr<-mkRegA(`IDCODEVALUE);
176
177 Wire#(Bool) wr_dmihardreset_generated<-mkDWire(False);
178 Reg#(Bit#(1)) rg_dmihardreset<-mkRegA(0);
179 Reg#(Bit#(1)) dmihardreset=condwriteSideEffect(rg_dmihardreset,wr_dmihardreset_generated._write(True));
180 Wire#(Bool) wr_dmireset_generated<-mkDWire(False);
181 Reg#(Bit#(1)) rg_dmireset<-mkDReg(0);
182 Reg#(Bit#(1)) dmireset=condwriteSideEffect(rg_dmireset,wr_dmireset_generated._write(True));
183 Reg#(Bit#(3)) idle=readOnlyReg(3'd7);
184 Reg#(Bit#(2)) dmistat<-mkRegA(0);
185 Reg#(Bit#(6)) abits =readOnlyReg(6'd6);
186 Reg#(Bit#(4)) version = readOnlyReg('d1);
187 Reg#(Bit#(32)) dtmcontrol=concatReg8(readOnlyReg(14'd0),
188 dmihardreset,dmireset,readOnlyReg(1'd0),
189 idle,readOnlyReg(dmistat),abits,version);
190 Reg#(Bit#(32)) dtmcontrol_shiftreg<-mkRegA({17'd0,3'd7,2'd0,6'd6,4'd1});
191
192 Reg#(Bit#(40)) dmiaccess_shiftreg[2]<-mkCReg(2,'d2);
193 Reg#(Bit#(2)) response_status<-mkReg(0);
194 Reg#(Bool) capture_repsonse_from_dm<-mkRegA(False);
195 Reg#(Bit#(1)) rg_tdo<-mkRegA(0, clocked_by invert_clock, reset_by invert_reset);
196
197 ReadOnly#(TapStates) crossed_tapstate <-mkNullCrossingWire(invert_clock,tapstate);
198 ReadOnly#(Bit#(5)) crossed_instruction_shiftreg<-mkNullCrossingWire(invert_clock,instruction_shiftreg);
199 ReadOnly#(Bit#(5)) crossed_instruction <-mkNullCrossingWire(def_clk,instruction);
200 ReadOnly#(Bit#(1)) crossed_scan_out_1_sr <-mkNullCrossingWire(invert_clock,scan_out_1_sr);
201 ReadOnly#(Bit#(1)) crossed_scan_out_2_sr <-mkNullCrossingWire(invert_clock,scan_out_2_sr);
202 ReadOnly#(Bit#(1)) crossed_scan_out_3_sr <-mkNullCrossingWire(invert_clock,scan_out_3_sr);
203 ReadOnly#(Bit#(1)) crossed_scan_out_4_sr <-mkNullCrossingWire(invert_clock,scan_out_4_sr);
204 ReadOnly#(Bit#(1)) crossed_scan_out_5_sr <-mkNullCrossingWire(invert_clock,scan_out_5_sr);
205 ReadOnly#(Bit#(1)) crossed_scan_en_sr <-mkNullCrossingWire(invert_clock,scan_en_sr);
206 ReadOnly#(Bit#(1)) crossed_scan_mode_te_sr <-mkNullCrossingWire(invert_clock,scan_mode_te_sr);
207 ReadOnly#(Bit#(1)) crossed_full_scan_en_sr <-mkNullCrossingWire(invert_clock,full_scan_en_sr);
208 ReadOnly#(Bit#(1)) crossed_bypass_sr <-mkNullCrossingWire(invert_clock,bypass_sr);
209 ReadOnly#(Bit#(32)) crossed_idcode_sr <-mkNullCrossingWire(invert_clock,idcode_sr);
210 ReadOnly#(Bit#(1)) crossed_bs_chain_tdo <-mkNullCrossingWire(invert_clock,wr_bs_chain_tdo);
211 ReadOnly#(Bit#(1)) crossed_debug_tdi <-mkNullCrossingWire(invert_clock,wr_debug_tdi);
212 ReadOnly#(Bit#(32)) crossed_dtmcontrol_shiftreg<-mkNullCrossingWire(invert_clock,dtmcontrol_shiftreg);
213 ReadOnly#(Bit#(1)) crossed_output_tdo<-mkNullCrossingWire(def_clk,rg_tdo);
214 ReadOnly#(Bit#(40)) crossed_dmiaccess_shiftreg<-mkNullCrossingWire(invert_clock,dmiaccess_shiftreg[0]);
215
216 Bit#(1) bypass_sel = crossed_instruction == `BYPASS?1:0;
217 Bit#(1) scan_en_sel = crossed_instruction == `SCANEN?1:0;
218 Bit#(1) scan_mode_te_sel = crossed_instruction == `SCANMODE_TE?1:0;
219 Bit#(1) scan1_sel = crossed_instruction == `SCAN1?1:0;
220 Bit#(1) scan2_sel = crossed_instruction == `SCAN2?1:0;
221 Bit#(1) scan3_sel = crossed_instruction == `SCAN3?1:0;
222 Bit#(1) scan4_sel = crossed_instruction == `SCAN4?1:0;
223 Bit#(1) scan5_sel = crossed_instruction == `SCAN5?1:0;
224 Bit#(1) scanall_sel = crossed_instruction == `SCANALL?1:0;
225 Bit#(1) full_scan_en_sel = crossed_instruction == `FULLSCANEN?1:0;
226 Bit#(1) idcode_sel = crossed_instruction == `IDCODE?1:0;
227 Bit#(1) dbg_sel = crossed_instruction == `DEBUG?1:0;
228 Bit#(1) dtmcontrol_sel = crossed_instruction == `DTMCONTROL?1:0;
229 Bit#(1) dmi_sel = crossed_instruction == `DMIACCESS?1:0;
230 Bit#(1) extest_select=crossed_instruction==`EXTEST?1:0;
231 Bit#(1) sample_preload_select=crossed_instruction==`SAMPLE_PRELOAD?1:0;
232
233 Bit#(1) instruction_tdo=crossed_instruction_shiftreg[0];
234 Bit#(1) bypass_tdo=crossed_bypass_sr;
235 Bit#(1) scan_en_tdo=crossed_scan_en_sr;
236 Bit#(1) scan_mode_te_tdo=crossed_scan_mode_te_sr;
237 Bit#(1) full_scan_en_tdo=crossed_full_scan_en_sr;
238 Bit#(1) scan_out_1_tdo=crossed_scan_out_1_sr;
239 Bit#(1) scan_out_2_tdo=crossed_scan_out_2_sr;
240 Bit#(1) scan_out_3_tdo=crossed_scan_out_3_sr;
241 Bit#(1) scan_out_4_tdo=crossed_scan_out_4_sr;
242 Bit#(1) scan_out_5_tdo=crossed_scan_out_5_sr;
243 Bit#(1) idcode_tdo=crossed_idcode_sr[0];
244 Bit#(1) dtmcontrol_tdo=crossed_dtmcontrol_shiftreg[0];
245 Bit#(1) dmiaccess_tdo=crossed_dmiaccess_shiftreg[0][0];
246
247
248
249 /*== This rule implements the TAPs STATE MACHINE====== */
250 rule just_display;
251 `ifdef verbose $display($time,"\tTAPSTATE: ",fshow(tapstate),"\tINSTRUCTION: %h",instruction_shiftreg); `endif
252 endrule
253 rule tap_state_machine;
254 case(tapstate)
255 TestLogicReset: if(wr_tms==0) tapstate<=RunTestIdle;
256 RunTestIdle : if(wr_tms==1) tapstate <= SelectDRScan;
257 SelectDRScan : if(wr_tms==1) tapstate <= SelectIRScan;
258 else tapstate <= CaptureDR;
259 CaptureDR : if(wr_tms==0) tapstate <= ShiftDR;
260 else tapstate <= Exit1DR;
261 ShiftDR : if(wr_tms==1) tapstate <= Exit1DR;
262 Exit1DR : if(wr_tms==0) tapstate <= PauseDR;
263 else tapstate <= UpdateDR;
264 PauseDR : if(wr_tms==1) tapstate <= Exit2DR;
265 Exit2DR : if(wr_tms==1) tapstate <= UpdateDR;
266 else tapstate <= ShiftDR;
267 UpdateDR : if(wr_tms==1) tapstate <= SelectDRScan;
268 else tapstate <= RunTestIdle;
269 SelectIRScan : if(wr_tms==1) tapstate <= TestLogicReset;
270 else tapstate <= CaptureIR;
271 CaptureIR : if(wr_tms==0) tapstate <= ShiftIR;
272 else tapstate <= Exit1IR;
273 ShiftIR : if(wr_tms==1) tapstate <= Exit1IR;
274 Exit1IR : if(wr_tms==0) tapstate <= PauseIR;
275 else tapstate <= UpdateIR;
276 PauseIR : if(wr_tms==1) tapstate <= Exit2IR;
277 Exit2IR : if(wr_tms==1) tapstate <= UpdateIR;
278 else tapstate <= ShiftIR;
279 UpdateIR : if(wr_tms==1) tapstate <= SelectDRScan;
280 else tapstate <= RunTestIdle;
281 default : tapstate <= TestLogicReset;
282 endcase
283 endrule
284
285 rule dmireset_generated(wr_dmireset_generated);
286 `ifdef verbose $display($time,"\tDTM: Received DMIRESET"); `endif
287 dmiaccess_shiftreg[1][1:0]<='d0;
288 response_status<=0;
289 capture_repsonse_from_dm<=False;
290 endrule
291 rule dmihardreset_generated(wr_dmihardreset_generated);
292 request_to_DM.deq;
293 response_from_DM.deq;
294 capture_repsonse_from_dm<=False;
295 endrule
296
297 /*======= perform dtmcontrol shifts ======== */
298 rule shift_dtm;
299 case(tapstate)
300 TestLogicReset: dtmcontrol<={17'd0,idle,2'b0,abits,version};
301 CaptureDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<=dtmcontrol;
302 ShiftDR: if(dtmcontrol_sel==1) dtmcontrol_shiftreg<={wr_tdi,dtmcontrol_shiftreg[31:1]};
303 UpdateDR: if(dtmcontrol_sel==1) dtmcontrol<=dtmcontrol_shiftreg;
304 endcase
305 endrule
306 /*========================================== */
307 /*======= perform dmiaccess shifts ======== */
308 rule shift_dmiaccess(!wr_dmihardreset_generated);
309 case(tapstate)
310 TestLogicReset: dmiaccess_shiftreg[0]<='d0;
311 CaptureDR: if(dmi_sel==1)
312 if(response_from_DM.notEmpty)begin
313 let x=response_from_DM.first[33:0];
314 `ifdef verbose $display($time,"\tDTM: Getting response: data %h op: %h",x[33:2],x[1:0]); `endif
315 x[1:0]=x[1:0]|response_status;// keeping the lower 2 bits sticky
316 dmiaccess_shiftreg[0][33:0]<=x;
317 response_status<=x[1:0];
318 response_from_DM.deq;
319 `ifdef verbose $display($time,"\tDTM: New DMIACCESS value: %h",x); `endif
320 capture_repsonse_from_dm<=False;
321 dmistat<=x[1:0];
322 end
323 else begin
324 if(capture_repsonse_from_dm)
325 response_status<=3;
326 `ifdef verbose $display($time,"\tDTM: RESPONSE NOT AVAILABLE. DMIACCESS: %h",dmiaccess_shiftreg[0]); `endif
327 end
328 ShiftDR: if(dmi_sel==1) dmiaccess_shiftreg[0]<={wr_tdi,dmiaccess_shiftreg[0][39:1]};
329 UpdateDR: if(dmi_sel==1)
330 if(request_to_DM.notFull && dmiaccess_shiftreg[0][1:0]!=0 && capture_repsonse_from_dm==False)begin
331 request_to_DM.enq(dmiaccess_shiftreg[0]);
332 dmiaccess_shiftreg[0][1:0]<='d3;
333 capture_repsonse_from_dm<=True;
334 `ifdef verbose $display($time,"\tDTM: Sending request to Debug: %h",dmiaccess_shiftreg[0]); `endif
335 end
336 else begin
337 `ifdef verbose $display($time,"\tDTM: REQUEST NOT SERVED capture: %b DMIACCESS: %h",capture_repsonse_from_dm,dmiaccess_shiftreg[0]); `endif
338 // dmistat<=3;
339 // response_from_DM.enq('d3);
340 end
341 endcase
342 endrule
343 /*========================================== */
344
345 /*== perform instruction register shifts === */
346 rule shift_reg;
347 case(tapstate)
348 CaptureIR: instruction_shiftreg<='b10101;
349 ShiftIR : instruction_shiftreg<= {wr_tdi,instruction_shiftreg[4:1]};
350 endcase
351 endrule
352 rule transfer_instruction_on_nedge; // TODO negedge here
353 case(crossed_tapstate)
354 TestLogicReset :instruction<=`IDCODE;
355 UpdateIR :instruction<=crossed_instruction_shiftreg;
356 endcase
357 endrule
358
359 /*==== Bypass Section === */
360 rule bypass_logic;
361 case(tapstate)
362 TestLogicReset: bypass_sr<=1'b0;
363 CaptureDR : if(bypass_sel==1) bypass_sr<=1'b0;
364 ShiftDR : if(bypass_sel==1) bypass_sr<=wr_tdi;
365 endcase
366 endrule
367
368 /*==== Boundary Scan Section === */
369 rule bs_logic;
370 case(tapstate)
371 TestLogicReset: bs_sr<=1'b0;
372 CaptureDR : begin
373 if(extest_select==1) begin
374 shiftBscan2Edge_sr <= 1'b0;
375 selectJtagInput_sr <= 1'b0;
376 selectJtagOutput_sr <= 1'b0;
377 updateBscan_sr <= 1'b0;
378 bs_sr<=1'b0;
379 end else if (sample_preload_select ==1) begin
380 shiftBscan2Edge_sr <= 1'b0;
381 selectJtagInput_sr <= 1'b0;
382 selectJtagOutput_sr <= 1'b0;
383 bs_sr<=1'b0;
384 end
385 end
386 ShiftDR : begin
387 if(extest_select==1) begin
388 shiftBscan2Edge_sr <= 1'b1;
389 selectJtagInput_sr <= 1'b0;
390 selectJtagOutput_sr <= 1'b0;
391 updateBscan_sr <= 1'b0;
392 bs_sr<=wr_tdi;
393 end else if (sample_preload_select ==1) begin
394 bs_sr<=wr_tdi;
395 shiftBscan2Edge_sr <= 1'b1;
396 end
397 end
398 UpdateDR : begin
399 if(extest_select==1) begin
400 shiftBscan2Edge_sr <= 1'b1;
401 selectJtagInput_sr <= 1'b1;
402 selectJtagOutput_sr <= 1'b1;
403 updateBscan_sr <= 1'b1;
404 end
405 end
406 endcase
407 endrule
408
409 /*==== Scan Chain Section === */
410 rule scan_logic;
411 case(tapstate)
412 TestLogicReset: begin
413 scan_en_sr<=1'b0;
414 scan_mode_te_sr<=1'b0;
415 scan1_sr<=1'b0;
416 scan2_sr<=1'b0;
417 scan3_sr<=1'b0;
418 scan4_sr<=1'b0;
419 scan5_sr<=1'b0;
420 scanall_sr<=1'b0;
421 full_scan_en_sr<=1'b0;
422 wr_scan_shift_en[0]<=1'b0;
423 end
424 CaptureDR : begin
425 if(scan_en_sel==1) scan_en_sr<=1'b0;
426 else if(scan_mode_te_sel==1) scan_mode_te_sr<=1'b0;
427 else if(scan1_sel==1) scan1_sr<=1'b0;
428 else if(scan2_sel==1) scan2_sr<=1'b0;
429 else if(scan3_sel==1) scan3_sr<=1'b0;
430 else if(scan4_sel==1) scan4_sr<=1'b0;
431 else if(scan5_sel==1) scan5_sr<=1'b0;
432 else if(scanall_sel==1) scanall_sr<=1'b0;
433 else if(full_scan_en_sel==1) full_scan_en_sr<=1'b0;
434 wr_scan_shift_en[0]<=1'b0;
435 end
436 ShiftDR : begin
437 if(scan_en_sel==1) scan_en_sr<=wr_tdi;
438 else if(scan_mode_te_sel==1) scan_mode_te_sr<=wr_tdi;
439 else if(scan1_sel==1) scan1_sr<=wr_tdi;
440 else if(scan2_sel==1) scan2_sr<=wr_tdi;
441 else if(scan3_sel==1) scan3_sr<=wr_tdi;
442 else if(scan4_sel==1) scan4_sr<=wr_tdi;
443 else if(scan5_sel==1) scan5_sr<=wr_tdi;
444 else if(scanall_sel==1) scanall_sr<=wr_tdi;
445 else if(full_scan_en_sel==1) full_scan_en_sr<=wr_tdi;
446 if ((scan1_sel == 1'b1 || scan2_sel == 1'b1|| scan3_sel == 1'b1|| scan4_sel == 1'b1|| scan5_sel == 1'b1|| scanall_sel == 1'b1) || (scan_en_sel == 1'b1 && wr_tdi == 1'b0)) wr_scan_shift_en[1] <=1'b1;
447 end
448 UpdateDR : wr_scan_shift_en[0] <=1'b0;
449 endcase
450 endrule
451
452 rule full_scan_mux_logic;
453 if (full_scan_en_sr == 1'b1) begin
454 wr_scan_in_1_all <= scanall_sr;
455 wr_scan_in_2_out1 <= scan_out_1_sr;
456 wr_scan_in_3_out2 <= scan_out_2_sr;
457 wr_scan_in_4_out3 <= scan_out_3_sr;
458 wr_scan_in_5_out4 <= scan_out_4_sr;
459 end
460 else begin
461 wr_scan_in_1_all <= scan1_sr;
462 wr_scan_in_2_out1 <= scan2_sr;
463 wr_scan_in_3_out2 <= scan3_sr;
464 wr_scan_in_4_out3 <= scan4_sr;
465 wr_scan_in_5_out4 <= scan5_sr;
466 end
467 endrule
468
469 /*======= IDCODE section === */
470 rule idcode_logic;
471 case(tapstate)
472 TestLogicReset:idcode_sr<=`IDCODEVALUE;
473 CaptureDR: if(idcode_sel==1) idcode_sr<=`IDCODEVALUE;
474 ShiftDR : if(idcode_sel==1) idcode_sr<={wr_tdi,idcode_sr[31:1]};
475 endcase
476 endrule
477
478 rule generate_tdo_outputpin;
479 if(crossed_tapstate==ShiftIR)
480 rg_tdo<=instruction_tdo;
481 else
482 case(instruction)
483 `IDCODE: rg_tdo<=idcode_tdo;
484 `DEBUG : rg_tdo<=crossed_debug_tdi;
485 `EXTEST: rg_tdo<=crossed_bs_chain_tdo;
486 `SAMPLE_PRELOAD: rg_tdo<=crossed_bs_chain_tdo;
487 `BYPASS: rg_tdo<=bypass_tdo;
488 `SCANEN: rg_tdo<=scan_en_tdo;
489 `SCANMODE_TE: rg_tdo<=scan_mode_te_tdo;
490 `FULLSCANEN: rg_tdo<=full_scan_en_tdo;
491 `SCAN1: rg_tdo <= scan_out_1_tdo;
492 `SCAN2: rg_tdo <= scan_out_2_tdo;
493 `SCAN3: rg_tdo <= scan_out_3_tdo;
494 `SCAN4: rg_tdo <= scan_out_4_tdo;
495 `SCAN5: rg_tdo <= scan_out_5_tdo;
496 `SCANALL: rg_tdo <= scan_out_5_tdo;
497 `DTMCONTROL: rg_tdo<=dtmcontrol_tdo;
498 `DMIACCESS: rg_tdo<=dmiaccess_tdo;
499 default: rg_tdo<=bypass_tdo;
500 endcase
501 endrule
502
503 /*======== SCAN input (scan chain outputs) pins ===== */
504 method Action scan_out_1_i(Bit#(1) scan_out_1);
505 scan_out_1_sr<=scan_out_1;
506 endmethod
507 method Action scan_out_2_i(Bit#(1) scan_out_2);
508 scan_out_2_sr<=scan_out_2;
509 endmethod
510 method Action scan_out_3_i(Bit#(1) scan_out_3);
511 scan_out_3_sr<=scan_out_3;
512 endmethod
513 method Action scan_out_4_i(Bit#(1) scan_out_4);
514 scan_out_4_sr<=scan_out_4;
515 endmethod
516 method Action scan_out_5_i(Bit#(1) scan_out_5);
517 scan_out_5_sr<=scan_out_5;
518 endmethod
519 /*======== JTAG input pins ===== */
520
521 interface tms = interface Put
522 method Action put(Bit#(1) in);
523 wr_tms<=in;
524 endmethod
525 endinterface;
526
527 interface tdi = interface Put
528 method Action put(Bit#(1) in);
529 wr_tdi<=in;
530 endmethod
531 endinterface;
532
533 /*============================= */
534 method Action debug_tdi_i(Bit#(1) debug_tdi);
535 wr_debug_tdi<=debug_tdi;
536 endmethod
537 /*======= Boundary Scan Input Pins ====== */
538 method Action bs_chain_i(Bit#(1) bs_chain);
539 wr_bs_chain_tdo<=bs_chain;
540 endmethod
541 /*======== TAP States ============= */
542 method shift_dr=tapstate==ShiftDR?1:0;
543 method pause_dr=tapstate==PauseDR?1:0;
544 method update_dr=tapstate==UpdateDR?1:0;
545 method capture_dr=tapstate==CaptureDR?1:0;
546 /*=================================== */
547 method debug_select =crossed_instruction==`DEBUG?1:0;
548 /*================================ */
549 /*======= SCAN Output (Scan Chain Inputs) Pins ====== */
550 method scan_in_1 = wr_scan_in_1_all;
551 method scan_in_2 = wr_scan_in_2_out1;
552 method scan_in_3 = wr_scan_in_3_out2;
553 method scan_in_4 = wr_scan_in_4_out3;
554 method scan_in_5 = wr_scan_in_5_out4;
555 method scan_en = scan_en_sr;
556 method scan_mode_te = scan_mode_te_sr;
557 /*======= Boundary Scan Output Pins ====== */
558 method shiftBscan2Edge = shiftBscan2Edge_sr;
559 method selectJtagInput = selectJtagInput_sr;
560 method selectJtagOutput = selectJtagOutput_sr;
561 method updateBscan = updateBscan_sr;
562 method bscan_in = bs_sr;
563 method scan_shift_en = wr_scan_shift_en[1];
564 /*======= JTAG Output Pins ====== */
565 interface tck = interface Get
566 method ActionValue#(Bit#(1)) get;
567 return ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
568 endmethod
569 endinterface;
570
571 interface tdo = interface Get
572 method ActionValue#(Bit#(1)) get;
573 return crossed_output_tdo;
574 endmethod
575 endinterface;
576
577 method debug_tdo = wr_tdi;
578 method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
579 if(capture_repsonse_from_dm)
580 response_from_DM.enq(responsedm);
581 endmethod
582 method ActionValue#(Bit#(40)) request_to_dm if(request_to_DM.notEmpty);
583 request_to_DM.deq;
584 return request_to_DM.first;
585 endmethod
586 endmodule
587
588 endpackage
Unnamed repository; edit this file 'description' to name the repository.